-
Notifications
You must be signed in to change notification settings - Fork 2
/
Copy pathAHB_APB_INTERFACE0.5.cr.mti
43 lines (31 loc) · 1.54 KB
/
AHB_APB_INTERFACE0.5.cr.mti
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
C:/intelFPGA/20.1/BRIDGE_TOP.v {1 {vlog -work work -stats=none C:/intelFPGA/20.1/BRIDGE_TOP.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module bridge_top
Top level modules:
bridge_top
} {} {}} C:/intelFPGA/20.1/APB_INTERFACE.v {1 {vlog -work work -stats=none C:/intelFPGA/20.1/APB_INTERFACE.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module apb_interface
Top level modules:
apb_interface
} {} {}} C:/intelFPGA/20.1/TOP_MODULE.v {1 {vlog -work work -stats=none {C:\intelFPGA\20.1\TOP_MODULE.v}
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module top
Top level modules:
top
} {} {}} C:/intelFPGA/20.1/AHB_SLAVE_INTERFACE.v {1 {vlog -work work -stats=none C:/intelFPGA/20.1/AHB_SLAVE_INTERFACE.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module ahb_slave_interface
Top level modules:
ahb_slave_interface
} {} {}} C:/intelFPGA/20.1/AHB_MASTER.v {1 {vlog -work work -stats=none C:/intelFPGA/20.1/AHB_MASTER.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module ahb_master
Top level modules:
ahb_master
} {} {}} C:/intelFPGA/20.1/APB_CONTROLLER.v {1 {vlog -work work -stats=none C:/intelFPGA/20.1/APB_CONTROLLER.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module apb_controller
Top level modules:
apb_controller
} {} {}}