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| 1 | +/* |
| 2 | + ******************************************************************************* |
| 3 | + * Copyright (c) 2020-2021, STMicroelectronics |
| 4 | + * All rights reserved. |
| 5 | + * |
| 6 | + * This software component is licensed by ST under BSD 3-Clause license, |
| 7 | + * the "License"; You may not use this file except in compliance with the |
| 8 | + * License. You may obtain a copy of the License at: |
| 9 | + * opensource.org/licenses/BSD-3-Clause |
| 10 | + * |
| 11 | + ******************************************************************************* |
| 12 | + */ |
| 13 | +#if defined(STM32H743xx) |
| 14 | +#include "pins_arduino.h" |
| 15 | + |
| 16 | +// Digital PinName array |
| 17 | +const PinName digitalPin[] = { |
| 18 | + PA_0, // D0/A0 |
| 19 | + PA_1, // D1/A1 |
| 20 | + PA_2, // D2/A2 |
| 21 | + PA_3, // D3/A3 |
| 22 | + PA_4, // D4/A4 |
| 23 | + PA_5, // D5/A5 |
| 24 | + PA_6, // D6/A6 |
| 25 | + PA_7, // D7/A7 |
| 26 | + PA_8, // D8 |
| 27 | + PA_9, // D9 |
| 28 | + PA_10, // D10 |
| 29 | + PA_11, // D11 |
| 30 | + PA_12, // D12 |
| 31 | + PA_13, // D13 |
| 32 | + PA_14, // D14 |
| 33 | + PA_15, // D15 |
| 34 | + PB_0, // D16/A8 |
| 35 | + PB_1, // D17/A9 |
| 36 | + PB_2, // D18 |
| 37 | + PB_3, // D19 |
| 38 | + PB_4, // D20 |
| 39 | + PB_5, // D21 |
| 40 | + PB_6, // D22 |
| 41 | + PB_7, // D23 |
| 42 | + PB_8, // D24 |
| 43 | + PB_9, // D25 |
| 44 | + PB_10, // D26 |
| 45 | + PB_11, // D27 |
| 46 | + PB_12, // D28 |
| 47 | + PB_13, // D29 |
| 48 | + PB_14, // D30 |
| 49 | + PB_15, // D31 |
| 50 | + PC_0, // D32/A10 |
| 51 | + PC_1, // D33/A11 |
| 52 | + PC_4, // D34/A12 |
| 53 | + PC_5, // D35/A13 |
| 54 | + PC_6, // D36 |
| 55 | + PC_7, // D37 |
| 56 | + PC_8, // D38 |
| 57 | + PC_9, // D39 |
| 58 | + PC_10, // D40 |
| 59 | + PC_11, // D41 |
| 60 | + PC_12, // D42 |
| 61 | + PC_13, // D43 |
| 62 | + PC_14, // D44 |
| 63 | + PC_15, // D45 |
| 64 | + PD_0, // D46 |
| 65 | + PD_1, // D47 |
| 66 | + PD_2, // D48 |
| 67 | + PD_3, // D49 |
| 68 | + PD_4, // D50 |
| 69 | + PD_5, // D51 |
| 70 | + PD_6, // D52 |
| 71 | + PD_7, // D53 |
| 72 | + PD_8, // D54 |
| 73 | + PD_9, // D55 |
| 74 | + PD_10, // D56 |
| 75 | + PD_11, // D57 |
| 76 | + PD_12, // D58 |
| 77 | + PD_13, // D59 |
| 78 | + PD_14, // D60 |
| 79 | + PD_15, // D61 |
| 80 | + PE_0, // D62 |
| 81 | + PE_1, // D63 |
| 82 | + PE_2, // D64 |
| 83 | + PE_3, // D65 |
| 84 | + PE_4, // D66 |
| 85 | + PE_5, // D67 |
| 86 | + PE_6, // D68 |
| 87 | + PE_7, // D69 |
| 88 | + PE_8, // D70 |
| 89 | + PE_9, // D71 |
| 90 | + PE_10, // D72 |
| 91 | + PE_11, // D73 |
| 92 | + PE_12, // D74 |
| 93 | + PE_13, // D75 |
| 94 | + PE_14, // D76 |
| 95 | + PE_15, // D77 |
| 96 | + PH_0, // D78 |
| 97 | + PH_1, // D79 |
| 98 | + PC_2_C, // D80/A14 |
| 99 | + PC_3_C // D81/A15 |
| 100 | +}; |
| 101 | + |
| 102 | +// Analog (Ax) pin number array |
| 103 | +const uint32_t analogInputPin[] = { |
| 104 | + 0, // A0, PA0 |
| 105 | + 1, // A1, PA1 |
| 106 | + 2, // A2, PA2 |
| 107 | + 3, // A3, PA3 |
| 108 | + 4, // A4, PA4 |
| 109 | + 5, // A5, PA5 |
| 110 | + 6, // A6, PA6 |
| 111 | + 7, // A7, PA7 |
| 112 | + 16, // A8, PB0 |
| 113 | + 17, // A9, PB1 |
| 114 | + 32, // A10, PC0 |
| 115 | + 33, // A11, PC1 |
| 116 | + 34, // A12, PC4 |
| 117 | + 35, // A13, PC5 |
| 118 | + 80, // A14, PC2_C |
| 119 | + 81 // A15, PC3_C |
| 120 | +}; |
| 121 | + |
| 122 | +/* |
| 123 | + * @brief System Clock Configuration |
| 124 | + * @param None |
| 125 | + * @retval None |
| 126 | + */ |
| 127 | +WEAK void SystemClock_Config(void) |
| 128 | +{ |
| 129 | + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
| 130 | + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
| 131 | + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; |
| 132 | + |
| 133 | + /** Supply configuration update enable |
| 134 | + */ |
| 135 | + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); |
| 136 | + /** Configure the main internal regulator output voltage |
| 137 | + */ |
| 138 | + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); |
| 139 | + |
| 140 | + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} |
| 141 | + /** Initializes the RCC Oscillators according to the specified parameters |
| 142 | + * in the RCC_OscInitTypeDef structure. |
| 143 | + */ |
| 144 | + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| 145 | + RCC_OscInitStruct.HSEState = RCC_HSE_ON; |
| 146 | + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| 147 | + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| 148 | + RCC_OscInitStruct.PLL.PLLM = 5; // 25Mhz / 5 = 5Mhz |
| 149 | + RCC_OscInitStruct.PLL.PLLN = 192; // 25Mhz / 5 * 192 = 960Mhz |
| 150 | + RCC_OscInitStruct.PLL.PLLP = 2; // 960Mhz / 2 = 480Mhz |
| 151 | + RCC_OscInitStruct.PLL.PLLQ = 20; // 960Mhz / 20 = 48Mhz for USB |
| 152 | + RCC_OscInitStruct.PLL.PLLR = 20; // unused |
| 153 | + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; |
| 154 | + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; |
| 155 | + RCC_OscInitStruct.PLL.PLLFRACN = 0; |
| 156 | + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| 157 | + { |
| 158 | + Error_Handler(); |
| 159 | + } |
| 160 | + /** Initializes the CPU, AHB and APB buses clocks |
| 161 | + */ |
| 162 | + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |
| 163 | + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |
| 164 | + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; |
| 165 | + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| 166 | + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; |
| 167 | + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; |
| 168 | + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; |
| 169 | + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; |
| 170 | + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; |
| 171 | + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; |
| 172 | + |
| 173 | + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) |
| 174 | + { |
| 175 | + Error_Handler(); |
| 176 | + } |
| 177 | + |
| 178 | + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_QSPI |
| 179 | + | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_ADC |
| 180 | + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USART16 |
| 181 | + | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_I2C123 |
| 182 | + | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI123 |
| 183 | + | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6; |
| 184 | + |
| 185 | + /* PLL1 qclk used for USB 48 Mhz */ |
| 186 | + /* PLL1 qclk also used for FMC, QUADSPI, SDMMC, RNG, SAI */ |
| 187 | + /* PLL2 pclk is needed for adc max 80 Mhz (p,q,r same) */ |
| 188 | + /* PLL2 pclk also used for LP timers 2,3,4,5, SPI 1,2,3 */ |
| 189 | + /* PLL2 qclk is needed for uart, can, spi4,5,6 80 Mhz */ |
| 190 | + /* PLL3 r clk is needed for i2c 80 Mhz (p,q,r same) */ |
| 191 | + PeriphClkInitStruct.PLL2.PLL2M = 15; // M DIV 15 vco 25 / 15 ~ 1.667 Mhz |
| 192 | + PeriphClkInitStruct.PLL2.PLL2N = 96; // N MUL 96 |
| 193 | + PeriphClkInitStruct.PLL2.PLL2P = 2; // P div 2 |
| 194 | + PeriphClkInitStruct.PLL2.PLL2Q = 2; // Q div 2 |
| 195 | + PeriphClkInitStruct.PLL2.PLL2R = 2; // R div 2 |
| 196 | + // RCC_PLL1VCIRANGE_0 Clock range frequency between 1 and 2 MHz |
| 197 | + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0; |
| 198 | + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM; |
| 199 | + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; |
| 200 | + PeriphClkInitStruct.PLL3.PLL3M = 15; // M DIV 15 vco 25 / 15 ~ 1.667 Mhz |
| 201 | + PeriphClkInitStruct.PLL3.PLL3N = 96; // N MUL 96 |
| 202 | + PeriphClkInitStruct.PLL3.PLL3P = 2; // P div 2 |
| 203 | + PeriphClkInitStruct.PLL3.PLL3Q = 2; // Q div 2 |
| 204 | + PeriphClkInitStruct.PLL3.PLL3R = 2; // R div 2 |
| 205 | + // RCC_PLL1VCIRANGE_0 Clock range frequency between 1 and 2 MHz |
| 206 | + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0; |
| 207 | + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOMEDIUM; |
| 208 | + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; |
| 209 | + // ADC from PLL2 pclk |
| 210 | + PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; |
| 211 | + // USB from PLL1 qclk |
| 212 | + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; |
| 213 | + // QSPI from PLL1 qclk |
| 214 | + PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL; |
| 215 | + // SDMMC from PLL1 qclk |
| 216 | + PeriphClkInitStruct.SdmmcClockSelection = 0; |
| 217 | + //PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; |
| 218 | + // LPUART from PLL2 qclk |
| 219 | + PeriphClkInitStruct.Lpuart1ClockSelection = 0; |
| 220 | + //PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2; |
| 221 | + // USART from PLL2 qclk |
| 222 | + PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_PLL2; |
| 223 | + // USART from PLL2 qclk |
| 224 | + PeriphClkInitStruct.Usart234578ClockSelection = 0; |
| 225 | + //PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL2; |
| 226 | + // I2C123 from PLL3 rclk |
| 227 | + PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_PLL3; |
| 228 | + // I2C4 from PLL3 rclk |
| 229 | + PeriphClkInitStruct.I2c4ClockSelection = 0; |
| 230 | + //PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PLL3; |
| 231 | + // SPI123 from PLL2 pclk |
| 232 | + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2; |
| 233 | + // SPI45 from PLL2 qclk |
| 234 | + PeriphClkInitStruct.Spi45ClockSelection = 0; |
| 235 | + //PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; |
| 236 | + // SPI6 from PLL2 qclk |
| 237 | + PeriphClkInitStruct.Spi6ClockSelection = 0; |
| 238 | + //PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL2; |
| 239 | + |
| 240 | + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { |
| 241 | + Error_Handler(); |
| 242 | + } |
| 243 | +} |
| 244 | + |
| 245 | +#endif /* ARDUINO_GENERIC_* */ |
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