ARM.qsf

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		ARM_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C5T144C8
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY single_cycle
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:03:09  OCTOBER 28, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_timing_analysis
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name CHECK_OUTPUTS OFF
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SETUP_HOLD_DETECTION OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_3 -to LED1
set_location_assignment PIN_7 -to LED2
set_location_assignment PIN_9 -to LED3
set_location_assignment PIN_17 -to clk
set_location_assignment PIN_144 -to enable
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to enable
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name TEXT_FILE inst.txt
set_global_assignment -name VERILOG_FILE alu2.v
set_global_assignment -name VERILOG_FILE ARM.v
set_global_assignment -name VERILOG_FILE Control.v
set_global_assignment -name VERILOG_FILE control_unit.v
set_global_assignment -name VERILOG_FILE extend.v
set_global_assignment -name VERILOG_FILE memory.v
set_global_assignment -name VERILOG_FILE register_file.v
set_global_assignment -name VERILOG_FILE shift2.v
set_global_assignment -name VERILOG_FILE shifter.v
set_global_assignment -name VERILOG_FILE single_cycle.v
set_global_assignment -name VERILOG_FILE shift.v
set_instance_assignment -name RESERVE_PIN "AS SIGNALPROBE OUTPUT" -to LED1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED1
set_instance_assignment -name RESERVE_PIN "AS SIGNALPROBE OUTPUT" -to LED2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED2
set_instance_assignment -name RESERVE_PIN "AS SIGNALPROBE OUTPUT" -to LED3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED3
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MISC_FILE "H:/ARM-SC/ARM.dpf"
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "ARM-clk.vwf"
set_global_assignment -name MISC_FILE "D:/Documents/FPGA/ARM-SC/ARM.dpf"