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‎3rd_party/CMSIS/Include/cmsis_armcc.h

+3-3
Original file line numberDiff line numberDiff line change
@@ -62,9 +62,9 @@
6262
#ifndef __STATIC_INLINE
6363
#define __STATIC_INLINE static __inline
6464
#endif
65-
#ifndef __STATIC_FORCEINLINE
65+
#ifndef __STATIC_FORCEINLINE
6666
#define __STATIC_FORCEINLINE static __forceinline
67-
#endif
67+
#endif
6868
#ifndef __NO_RETURN
6969
#define __NO_RETURN __declspec(noreturn)
7070
#endif
@@ -472,7 +472,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
472472
__schedule_barrier();\
473473
} while (0U)
474474

475-
475+
476476
/**
477477
\brief Reverse byte order (32 bit)
478478
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

‎3rd_party/CMSIS/Include/cmsis_armclang.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -594,7 +594,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
594594
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
595595
Stack Pointer Limit register hence zero is returned always in non-secure
596596
mode.
597-
597+
598598
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
599599
\return PSPLIM Register value
600600
*/
@@ -640,7 +640,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
640640
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
641641
Stack Pointer Limit register hence the write is silently ignored in non-secure
642642
mode.
643-
643+
644644
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
645645
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
646646
*/

‎3rd_party/CMSIS/Include/cmsis_armclang_ltm.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -595,7 +595,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
595595
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
596596
Stack Pointer Limit register hence zero is returned always in non-secure
597597
mode.
598-
598+
599599
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
600600
\return PSPLIM Register value
601601
*/
@@ -641,7 +641,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
641641
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
642642
Stack Pointer Limit register hence the write is silently ignored in non-secure
643643
mode.
644-
644+
645645
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
646646
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
647647
*/

‎3rd_party/CMSIS/Include/cmsis_gcc.h

+12-12
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,9 @@
4646
#ifndef __STATIC_INLINE
4747
#define __STATIC_INLINE static inline
4848
#endif
49-
#ifndef __STATIC_FORCEINLINE
49+
#ifndef __STATIC_FORCEINLINE
5050
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51-
#endif
51+
#endif
5252
#ifndef __NO_RETURN
5353
#define __NO_RETURN __attribute__((__noreturn__))
5454
#endif
@@ -126,23 +126,23 @@
126126
\details This default implementations initialized all data and additional bss
127127
sections relying on .copy.table and .zero.table specified properly
128128
in the used linker script.
129-
129+
130130
*/
131131
__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
132132
{
133133
extern void _start(void) __NO_RETURN;
134-
134+
135135
typedef struct {
136136
uint32_t const* src;
137137
uint32_t* dest;
138138
uint32_t wlen;
139139
} __copy_table_t;
140-
140+
141141
typedef struct {
142142
uint32_t* dest;
143143
uint32_t wlen;
144144
} __zero_table_t;
145-
145+
146146
extern const __copy_table_t __copy_table_start__;
147147
extern const __copy_table_t __copy_table_end__;
148148
extern const __zero_table_t __zero_table_start__;
@@ -153,16 +153,16 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
153153
pTable->dest[i] = pTable->src[i];
154154
}
155155
}
156-
156+
157157
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
158158
for(uint32_t i=0u; i<pTable->wlen; ++i) {
159159
pTable->dest[i] = 0u;
160160
}
161161
}
162-
162+
163163
_start();
164164
}
165-
165+
166166
#define __PROGRAM_START __cmsis_start
167167
#endif
168168

@@ -652,7 +652,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
652652
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
653653
Stack Pointer Limit register hence zero is returned always in non-secure
654654
mode.
655-
655+
656656
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
657657
\return PSPLIM Register value
658658
*/
@@ -697,7 +697,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
697697
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
698698
Stack Pointer Limit register hence the write is silently ignored in non-secure
699699
mode.
700-
700+
701701
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
702702
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
703703
*/
@@ -834,7 +834,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
834834
{
835835
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
836836
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
837-
#if __has_builtin(__builtin_arm_get_fpscr)
837+
#if __has_builtin(__builtin_arm_get_fpscr)
838838
// Re-enable using built-in when GCC has been fixed
839839
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
840840
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

‎3rd_party/CMSIS/Include/cmsis_iccarm.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
//------------------------------------------------------------------------------
99
//
1010
// Copyright (c) 2017-2019 IAR Systems
11-
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
11+
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
1212
//
1313
// Licensed under the Apache License, Version 2.0 (the "License")
1414
// you may not use this file except in compliance with the License.

‎3rd_party/CMSIS/Include/core_armv81mml.h

+9-9
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@
6161
*/
6262

6363
#include "cmsis_version.h"
64-
64+
6565
#define __ARM_ARCH_8M_MAIN__ 1 // patching for now
6666
/* CMSIS ARMV81MML definitions */
6767
#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
@@ -91,12 +91,12 @@
9191
#define __DSP_USED 1U
9292
#else
9393
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
94-
#define __DSP_USED 0U
94+
#define __DSP_USED 0U
9595
#endif
9696
#else
9797
#define __DSP_USED 0U
9898
#endif
99-
99+
100100
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
101101
#if defined __ARM_FP
102102
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
@@ -114,7 +114,7 @@
114114
#define __DSP_USED 1U
115115
#else
116116
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
117-
#define __DSP_USED 0U
117+
#define __DSP_USED 0U
118118
#endif
119119
#else
120120
#define __DSP_USED 0U
@@ -131,18 +131,18 @@
131131
#else
132132
#define __FPU_USED 0U
133133
#endif
134-
134+
135135
#if defined(__ARM_FEATURE_DSP)
136136
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
137137
#define __DSP_USED 1U
138138
#else
139139
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
140-
#define __DSP_USED 0U
140+
#define __DSP_USED 0U
141141
#endif
142142
#else
143143
#define __DSP_USED 0U
144144
#endif
145-
145+
146146
#elif defined ( __ICCARM__ )
147147
#if defined __ARMVFP__
148148
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
@@ -160,12 +160,12 @@
160160
#define __DSP_USED 1U
161161
#else
162162
#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
163-
#define __DSP_USED 0U
163+
#define __DSP_USED 0U
164164
#endif
165165
#else
166166
#define __DSP_USED 0U
167167
#endif
168-
168+
169169
#elif defined ( __TI_ARM__ )
170170
#if defined __TI_VFP_SUPPORT__
171171
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)

‎3rd_party/CMSIS/Include/core_cm0.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@
6161
*/
6262

6363
#include "cmsis_version.h"
64-
64+
6565
/* CMSIS CM0 definitions */
6666
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
6767
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */

‎3rd_party/CMSIS/Include/core_cm0plus.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@
6161
*/
6262

6363
#include "cmsis_version.h"
64-
64+
6565
/* CMSIS CM0+ definitions */
6666
#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
6767
#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */

‎3rd_party/CMSIS/Include/core_cm1.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@
6161
*/
6262

6363
#include "cmsis_version.h"
64-
64+
6565
/* CMSIS CM1 definitions */
6666
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
6767
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */

‎3rd_party/CMSIS/Include/core_cm23.h

+3-3
Original file line numberDiff line numberDiff line change
@@ -1289,7 +1289,7 @@ typedef struct
12891289

12901290
/* Special LR values for Secure/Non-Secure call handling and exception handling */
12911291

1292-
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1292+
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
12931293
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
12941294

12951295
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
@@ -1304,11 +1304,11 @@ typedef struct
13041304
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
13051305
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
13061306
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
1307-
#else
1307+
#else
13081308
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
13091309
#endif
13101310

1311-
1311+
13121312
/* Interrupt Priorities are WORD accessible only under Armv6-M */
13131313
/* The following MACROS handle generation of the register offset and byte masks */
13141314
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)

‎3rd_party/CMSIS/Include/core_cm33.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -2064,7 +2064,7 @@ typedef struct
20642064

20652065
/* Special LR values for Secure/Non-Secure call handling and exception handling */
20662066

2067-
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2067+
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
20682068
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
20692069

20702070
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
@@ -2079,7 +2079,7 @@ typedef struct
20792079
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
20802080
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
20812081
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2082-
#else
2082+
#else
20832083
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
20842084
#endif
20852085

‎3rd_party/CMSIS/Include/core_cm35p.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -2064,7 +2064,7 @@ typedef struct
20642064

20652065
/* Special LR values for Secure/Non-Secure call handling and exception handling */
20662066

2067-
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2067+
/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
20682068
#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
20692069

20702070
/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
@@ -2079,7 +2079,7 @@ typedef struct
20792079
/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
20802080
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
20812081
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2082-
#else
2082+
#else
20832083
#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
20842084
#endif
20852085

‎3rd_party/CMSIS/Include/core_cm7.h

+6-6
Original file line numberDiff line numberDiff line change
@@ -2512,10 +2512,10 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
25122512
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
25132513
{
25142514
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2515-
if ( dsize > 0 ) {
2515+
if ( dsize > 0 ) {
25162516
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
25172517
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
2518-
2518+
25192519
__DSB();
25202520

25212521
do {
@@ -2542,10 +2542,10 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsiz
25422542
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
25432543
{
25442544
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2545-
if ( dsize > 0 ) {
2545+
if ( dsize > 0 ) {
25462546
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
25472547
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
2548-
2548+
25492549
__DSB();
25502550

25512551
do {
@@ -2572,10 +2572,10 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize
25722572
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
25732573
{
25742574
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
2575-
if ( dsize > 0 ) {
2575+
if ( dsize > 0 ) {
25762576
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
25772577
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
2578-
2578+
25792579
__DSB();
25802580

25812581
do {

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