passing empty dict to dag_to_circuit when None

alexanderivrii · alexanderivrii · commit 12c665df0d39 · 2025-02-09T16:21:46.000+02:00
diff --git a/qiskit/converters/dag_to_circuit.py b/qiskit/converters/dag_to_circuit.py
@@ -70,7 +70,7 @@ def dag_to_circuit(dag, copy_operations=True):
     )
     for var in dag.iter_declared_vars():
         circuit.add_uninitialized_var(var)
-    circuit.metadata = dag.metadata
+    circuit.metadata = dag.metadata or dict()
     circuit._calibrations_prop = dag._calibrations_prop
 
     circuit._data = circuit_data
diff --git a/qiskit/transpiler/passes/synthesis/high_level_synthesis.py b/qiskit/transpiler/passes/synthesis/high_level_synthesis.py
@@ -35,6 +35,7 @@
     HighLevelSynthesisData,
     py_run_on_dag,
 )
+
 from .plugin import HighLevelSynthesisPluginManager
 
 if typing.TYPE_CHECKING:

Original file line number	Diff line number	Diff line change
`@@ -70,7 +70,7 @@ def dag_to_circuit(dag, copy_operations=True):`
`70`	`70`	`)`
`71`	`71`	`for var in dag.iter_declared_vars():`
`72`	`72`	`circuit.add_uninitialized_var(var)`
`73`		`- circuit.metadata = dag.metadata`
	`73`	`+ circuit.metadata = dag.metadata or dict()`
`74`	`74`	`circuit._calibrations_prop = dag._calibrations_prop`
`75`	`75`
`76`	`76`	`circuit._data = circuit_data`
Original file line number	Diff line number	Diff line change
`@@ -35,6 +35,7 @@`
`35`	`35`	`HighLevelSynthesisData,`
`36`	`36`	`py_run_on_dag,`
`37`	`37`	`)`
	`38`	`+`
`38`	`39`	`from .plugin import HighLevelSynthesisPluginManager`
`39`	`40`
`40`	`41`	`if typing.TYPE_CHECKING:`