forked from SuperDisk/hUGEDriver
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathhardware.inc
1082 lines (912 loc) · 25.9 KB
/
hardware.inc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
;*
;* Gameboy Hardware definitions
;*
;* Based on Jones' hardware.inc
;* And based on Carsten Sorensen's ideas.
;*
;* Rev 1.1 - 15-Jul-97 : Added define check
;* Rev 1.2 - 18-Jul-97 : Added revision check macro
;* Rev 1.3 - 19-Jul-97 : Modified for RGBASM V1.05
;* Rev 1.4 - 27-Jul-97 : Modified for new subroutine prefixes
;* Rev 1.5 - 15-Aug-97 : Added _HRAM, PAD, CART defines
;* : and Nintendo Logo
;* Rev 1.6 - 30-Nov-97 : Added rDIV, rTIMA, rTMA, & rTAC
;* Rev 1.7 - 31-Jan-98 : Added _SCRN0, _SCRN1
;* Rev 1.8 - 15-Feb-98 : Added rSB, rSC
;* Rev 1.9 - 16-Feb-98 : Converted I/O registers to $FFXX format
;* Rev 2.0 - : Added GBC registers
;* Rev 2.1 - : Added MBC5 & cart RAM enable/disable defines
;* Rev 2.2 - : Fixed NR42,NR43, & NR44 equates
;* Rev 2.3 - : Fixed incorrect _HRAM equate
;* Rev 2.4 - 27-Apr-13 : Added some cart defines (AntonioND)
;* Rev 2.5 - 03-May-15 : Fixed format (AntonioND)
;* Rev 2.6 - 09-Apr-16 : Added GBC OAM and cart defines (AntonioND)
;* Rev 2.7 - 19-Jan-19 : Added rPCMXX (ISSOtm)
;* Rev 2.8 - 03-Feb-19 : Added audio registers flags (Álvaro Cuesta)
;* Rev 2.9 - 28-Feb-20 : Added utility rP1 constants
;* Rev 3.0 - 27-Aug-20 : Register ordering, byte-based sizes, OAM additions, general cleanup (Blitter Object)
;* Rev 4.0 - 03-May-21 : Updated to use RGBDS 0.5.0 syntax, changed IEF_LCDC to IEF_STAT (Eievui)
IF __RGBDS_MAJOR__ == 0 && __RGBDS_MINOR__ < 5
FAIL "This version of 'hardware.inc' requires RGBDS version 0.5.0 or later."
ENDC
; If all of these are already defined, don't do it again.
IF !DEF(HARDWARE_INC)
DEF HARDWARE_INC EQU 1
MACRO rev_Check_hardware_inc
;NOTE: REVISION NUMBER CHANGES MUST BE ADDED
;TO SECOND PARAMETER IN FOLLOWING LINE.
IF \1 > 4.0 ;PUT REVISION NUMBER HERE
WARN "Version \1 or later of 'hardware.inc' is required."
ENDC
ENDM
DEF _VRAM EQU $8000 ; $8000->$9FFF
DEF _VRAM8000 EQU _VRAM
DEF _VRAM8800 EQU _VRAM+$800
DEF _VRAM9000 EQU _VRAM+$1000
DEF _SCRN0 EQU $9800 ; $9800->$9BFF
DEF _SCRN1 EQU $9C00 ; $9C00->$9FFF
DEF _SRAM EQU $A000 ; $A000->$BFFF
DEF _RAM EQU $C000 ; $C000->$CFFF / $C000->$DFFF
DEF _RAMBANK EQU $D000 ; $D000->$DFFF
DEF _OAMRAM EQU $FE00 ; $FE00->$FE9F
DEF _IO EQU $FF00 ; $FF00->$FF7F,$FFFF
DEF _AUD3WAVERAM EQU $FF30 ; $FF30->$FF3F
DEF _HRAM EQU $FF80 ; $FF80->$FFFE
; *** MBC5 Equates ***
DEF rRAMG EQU $0000 ; $0000->$1fff
if def(TARGET_MEGADUCK)
DEF rROMB0 EQU $0001 ; $0001->$0001
else
DEF rROMB0 EQU $2000 ; $2000->$2fff
endc
DEF rROMB1 EQU $3000 ; $3000->$3fff - If more than 256 ROM banks are present.
DEF rRAMB EQU $4000 ; $4000->$5fff - Bit 3 enables rumble (if present)
;***************************************************************************
;*
;* Custom registers
;*
;***************************************************************************
; --
; -- P1 ($FF00)
; -- Register for reading joy pad info. (R/W)
; --
DEF rP1 EQU $FF00
DEF P1F_5 EQU %00100000 ; P15 out port, set to 0 to get buttons
DEF P1F_4 EQU %00010000 ; P14 out port, set to 0 to get dpad
DEF P1F_3 EQU %00001000 ; P13 in port
DEF P1F_2 EQU %00000100 ; P12 in port
DEF P1F_1 EQU %00000010 ; P11 in port
DEF P1F_0 EQU %00000001 ; P10 in port
DEF P1F_GET_DPAD EQU P1F_5
DEF P1F_GET_BTN EQU P1F_4
DEF P1F_GET_NONE EQU P1F_4 | P1F_5
; --
; -- SB ($FF01)
; -- Serial Transfer Data (R/W)
; --
DEF rSB EQU $FF01
; --
; -- SC ($FF02)
; -- Serial I/O Control (R/W)
; --
DEF rSC EQU $FF02
; --
; -- DIV ($FF04)
; -- Divider register (R/W)
; --
DEF rDIV EQU $FF04
; --
; -- TIMA ($FF05)
; -- Timer counter (R/W)
; --
DEF rTIMA EQU $FF05
; --
; -- TMA ($FF06)
; -- Timer modulo (R/W)
; --
DEF rTMA EQU $FF06
; --
; -- TAC ($FF07)
; -- Timer control (R/W)
; --
DEF rTAC EQU $FF07
DEF TACF_START EQU %00000100
DEF TACF_STOP EQU %00000000
DEF TACF_4KHZ EQU %00000000
DEF TACF_16KHZ EQU %00000011
DEF TACF_65KHZ EQU %00000010
DEF TACF_262KHZ EQU %00000001
; --
; -- IF ($FF0F)
; -- Interrupt Flag (R/W)
; --
DEF rIF EQU $FF0F
; --
; -- AUD1SWEEP/NR10 ($FF10)
; -- Sweep register (R/W)
; --
; -- Bit 6-4 - Sweep Time
; -- Bit 3 - Sweep Increase/Decrease
; -- 0: Addition (frequency increases???)
; -- 1: Subtraction (frequency increases???)
; -- Bit 2-0 - Number of sweep shift (# 0-7)
; -- Sweep Time: (n*7.8ms)
; --
if def(TARGET_MEGADUCK)
DEF rNR10 EQU $FF20
else
DEF rNR10 EQU $FF10
endc
DEF rAUD1SWEEP EQU rNR10
DEF AUD1SWEEP_UP EQU %00000000
DEF AUD1SWEEP_DOWN EQU %00001000
; --
; -- AUD1LEN/NR11 ($FF11)
; -- Sound length/Wave pattern duty (R/W)
; --
; -- Bit 7-6 - Wave Pattern Duty (00:12.5% 01:25% 10:50% 11:75%)
; -- Bit 5-0 - Sound length data (# 0-63)
; --
if def(TARGET_MEGADUCK)
DEF rNR11 EQU $FF22
else
DEF rNR11 EQU $FF11
endc
DEF rAUD1LEN EQU rNR11
; --
; -- AUD1ENV/NR12 ($FF12)
; -- Envelope (R/W)
; --
; -- Bit 7-4 - Initial value of envelope
; -- Bit 3 - Envelope UP/DOWN
; -- 0: Decrease
; -- 1: Range of increase
; -- Bit 2-0 - Number of envelope sweep (# 0-7)
; --
if def(TARGET_MEGADUCK)
DEF rNR12 EQU $FF21
else
DEF rNR12 EQU $FF12
endc
DEF rAUD1ENV EQU rNR12
; --
; -- AUD1LOW/NR13 ($FF13)
; -- Frequency low byte (W)
; --
if def(TARGET_MEGADUCK)
DEF rNR13 EQU $FF23
else
DEF rNR13 EQU $FF13
endc
DEF rAUD1LOW EQU rNR13
; --
; -- AUD1HIGH/NR14 ($FF14)
; -- Frequency high byte (W)
; --
; -- Bit 7 - Initial (when set, sound restarts)
; -- Bit 6 - Counter/consecutive selection
; -- Bit 2-0 - Frequency's higher 3 bits
; --
if def(TARGET_MEGADUCK)
DEF rNR14 EQU $FF24
else
DEF rNR14 EQU $FF14
endc
DEF rAUD1HIGH EQU rNR14
; --
; -- AUD2LEN/NR21 ($FF16)
; -- Sound Length; Wave Pattern Duty (R/W)
; --
; -- see AUD1LEN for info
; --
if def(TARGET_MEGADUCK)
DEF rNR21 EQU $FF25
else
DEF rNR21 EQU $FF16
endc
DEF rAUD2LEN EQU rNR21
; --
; -- AUD2ENV/NR22 ($FF17)
; -- Envelope (R/W)
; --
; -- see AUD1ENV for info
; --
if def(TARGET_MEGADUCK)
DEF rNR22 EQU $FF27
else
DEF rNR22 EQU $FF17
endc
DEF rAUD2ENV EQU rNR22
; --
; -- AUD2LOW/NR23 ($FF18)
; -- Frequency low byte (W)
; --
if def(TARGET_MEGADUCK)
DEF rNR23 EQU $FF28
else
DEF rNR23 EQU $FF18
endc
DEF rAUD2LOW EQU rNR23
; --
; -- AUD2HIGH/NR24 ($FF19)
; -- Frequency high byte (W)
; --
; -- see AUD1HIGH for info
; --
if def(TARGET_MEGADUCK)
DEF rNR24 EQU $FF29
else
DEF rNR24 EQU $FF19
endc
DEF rAUD2HIGH EQU rNR24
; --
; -- AUD3ENA/NR30 ($FF1A)
; -- Sound on/off (R/W)
; --
; -- Bit 7 - Sound ON/OFF (1=ON,0=OFF)
; --
if def(TARGET_MEGADUCK)
DEF rNR30 EQU $FF2A
else
DEF rNR30 EQU $FF1A
endc
DEF rAUD3ENA EQU rNR30
; --
; -- AUD3LEN/NR31 ($FF1B)
; -- Sound length (R/W)
; --
; -- Bit 7-0 - Sound length
; --
if def(TARGET_MEGADUCK)
DEF rNR31 EQU $FF2B
else
DEF rNR31 EQU $FF1B
endc
DEF rAUD3LEN EQU rNR31
; --
; -- AUD3LEVEL/NR32 ($FF1C)
; -- Select output level
; --
; -- Bit 6-5 - Select output level
; -- Game Boy:
; -- 00: 0/1 (mute)
; -- 01: 1/1
; -- 10: 1/2
; -- 11: 1/4
; -- MegaDuck:
; -- 00: 0/1 (mute)
; -- 01: 1/4 *
; -- 10: 1/2
; -- 11: 1/1 *
; --
if def(TARGET_MEGADUCK)
DEF rNR32 EQU $FF2C
else
DEF rNR32 EQU $FF1C
endc
DEF rAUD3LEVEL EQU rNR32
if def(TARGET_MEGADUCK)
DEF AUDVOL_CH3_OFF EQU %00000000
DEF AUDVOL_CH3_LO EQU %00100000
DEF AUDVOL_CH3_MED EQU %01000000
DEF AUDVOL_CH3_HI EQU %01100000
else
DEF AUDVOL_CH3_OFF EQU %00000000
DEF AUDVOL_CH3_LO EQU %01100000
DEF AUDVOL_CH3_MED EQU %01000000
DEF AUDVOL_CH3_HI EQU %00100000
endc
; --
; -- AUD3LOW/NR33 ($FF1D)
; -- Frequency low byte (W)
; --
; -- see AUD1LOW for info
; --
if def(TARGET_MEGADUCK)
DEF rNR33 EQU $FF2E
else
DEF rNR33 EQU $FF1D
endc
DEF rAUD3LOW EQU rNR33
; --
; -- AUD3HIGH/NR34 ($FF1E)
; -- Frequency high byte (W)
; --
; -- see AUD1HIGH for info
; --
if def(TARGET_MEGADUCK)
DEF rNR34 EQU $FF2D
else
DEF rNR34 EQU $FF1E
endc
DEF rAUD3HIGH EQU rNR34
; --
; -- AUD4LEN/NR41 ($FF20)
; -- Sound length (R/W)
; --
; -- Bit 5-0 - Sound length data (# 0-63)
; --
if def(TARGET_MEGADUCK)
DEF rNR41 EQU $FF40
else
DEF rNR41 EQU $FF20
endc
DEF rAUD4LEN EQU rNR41
; --
; -- AUD4ENV/NR42 ($FF21)
; -- Envelope (R/W)
; --
; -- see AUD1ENV for info
; --
if def(TARGET_MEGADUCK)
DEF rNR42 EQU $FF42
else
DEF rNR42 EQU $FF21
endc
DEF rAUD4ENV EQU rNR42
; --
; -- AUD4POLY/NR43 ($FF22)
; -- Polynomial counter (R/W)
; --
; -- Bit 7-4 - Selection of the shift clock frequency of the (scf)
; -- polynomial counter (0000-1101)
; -- freq=drf*1/2^scf (not sure)
; -- Bit 3 - Selection of the polynomial counter's step
; -- 0: 15 steps
; -- 1: 7 steps
; -- Bit 2-0 - Selection of the dividing ratio of frequencies (drf)
; -- 000: f/4 001: f/8 010: f/16 011: f/24
; -- 100: f/32 101: f/40 110: f/48 111: f/56 (f=4.194304 Mhz)
; --
if def(TARGET_MEGADUCK)
DEF rNR43 EQU $FF41
else
DEF rNR43 EQU $FF22
endc
DEF rAUD4POLY EQU rNR43
; --
; -- AUD4GO/NR44 ($FF23)
; --
; -- Bit 7 - Inital
; -- Bit 6 - Counter/consecutive selection
; --
if def(TARGET_MEGADUCK)
DEF rNR44 EQU $FF43
else
DEF rNR44 EQU $FF23
endc
DEF rAUD4GO EQU rNR44
; --
; -- AUDVOL/NR50 ($FF24)
; -- Channel control / ON-OFF / Volume (R/W)
; --
; -- Bit 7 - Vin->SO2 ON/OFF (Vin??)
; -- Bit 6-4 - SO2 output level (volume) (# 0-7)
; -- Bit 3 - Vin->SO1 ON/OFF (Vin??)
; -- Bit 2-0 - SO1 output level (volume) (# 0-7)
; --
if def(TARGET_MEGADUCK)
DEF rNR50 EQU $FF44
else
DEF rNR50 EQU $FF24
endc
DEF rAUDVOL EQU rNR50
DEF AUDVOL_VIN_LEFT EQU %10000000 ; SO2
DEF AUDVOL_VIN_RIGHT EQU %00001000 ; SO1
; --
; -- AUDTERM/NR51 ($FF25)
; -- Selection of Sound output terminal (R/W)
; --
; -- Bit 7 - Output sound 4 to SO2 terminal
; -- Bit 6 - Output sound 3 to SO2 terminal
; -- Bit 5 - Output sound 2 to SO2 terminal
; -- Bit 4 - Output sound 1 to SO2 terminal
; -- Bit 3 - Output sound 4 to SO1 terminal
; -- Bit 2 - Output sound 3 to SO1 terminal
; -- Bit 1 - Output sound 2 to SO1 terminal
; -- Bit 0 - Output sound 0 to SO1 terminal
; --
if def(TARGET_MEGADUCK)
DEF rNR51 EQU $FF46
else
DEF rNR51 EQU $FF25
endc
DEF rAUDTERM EQU rNR51
; SO2
DEF AUDTERM_4_LEFT EQU %10000000
DEF AUDTERM_3_LEFT EQU %01000000
DEF AUDTERM_2_LEFT EQU %00100000
DEF AUDTERM_1_LEFT EQU %00010000
; SO1
DEF AUDTERM_4_RIGHT EQU %00001000
DEF AUDTERM_3_RIGHT EQU %00000100
DEF AUDTERM_2_RIGHT EQU %00000010
DEF AUDTERM_1_RIGHT EQU %00000001
; --
; -- AUDENA/NR52 ($FF26)
; -- Sound on/off (R/W)
; --
; -- Bit 7 - All sound on/off (sets all audio regs to 0!)
; -- Bit 3 - Sound 4 ON flag (read only)
; -- Bit 2 - Sound 3 ON flag (read only)
; -- Bit 1 - Sound 2 ON flag (read only)
; -- Bit 0 - Sound 1 ON flag (read only)
; --
if def(TARGET_MEGADUCK)
DEF rNR52 EQU $FF45
else
DEF rNR52 EQU $FF26
endc
DEF rAUDENA EQU rNR52
DEF AUDENA_ON EQU %10000000
DEF AUDENA_OFF EQU %00000000 ; sets all audio regs to 0!
; --
; -- LCDC ($FF40)
; -- LCD Control (R/W)
; --
if def(TARGET_MEGADUCK)
DEF rLCDC EQU $FF10
DEF LCDCF_OFF EQU %00000000 ; LCD Control Operation
DEF LCDCF_ON EQU %10000000 ; LCD Control Operation
DEF LCDCF_WIN9800 EQU %00000000 ; Window Tile Map Display Select
DEF LCDCF_WIN9C00 EQU %00001000 ; Window Tile Map Display Select
DEF LCDCF_WINOFF EQU %00000000 ; Window Display
DEF LCDCF_WINON EQU %00100000 ; Window Display
DEF LCDCF_BG8800 EQU %00000000 ; BG & Window Tile Data Select
DEF LCDCF_BG8000 EQU %00010000 ; BG & Window Tile Data Select
DEF LCDCF_BG9800 EQU %00000000 ; BG Tile Map Display Select
DEF LCDCF_BG9C00 EQU %00000100 ; BG Tile Map Display Select
DEF LCDCF_OBJ8 EQU %00000000 ; OBJ Construction
DEF LCDCF_OBJ16 EQU %00000010 ; OBJ Construction
DEF LCDCF_OBJOFF EQU %00000000 ; OBJ Display
DEF LCDCF_OBJON EQU %00000001 ; OBJ Display
DEF LCDCF_BGOFF EQU %00000000 ; BG Display
DEF LCDCF_BGON EQU %01000000 ; BG Display
else
DEF rLCDC EQU $FF40
DEF LCDCF_OFF EQU %00000000 ; LCD Control Operation
DEF LCDCF_ON EQU %10000000 ; LCD Control Operation
DEF LCDCF_WIN9800 EQU %00000000 ; Window Tile Map Display Select
DEF LCDCF_WIN9C00 EQU %01000000 ; Window Tile Map Display Select
DEF LCDCF_WINOFF EQU %00000000 ; Window Display
DEF LCDCF_WINON EQU %00100000 ; Window Display
DEF LCDCF_BG8800 EQU %00000000 ; BG & Window Tile Data Select
DEF LCDCF_BG8000 EQU %00010000 ; BG & Window Tile Data Select
DEF LCDCF_BG9800 EQU %00000000 ; BG Tile Map Display Select
DEF LCDCF_BG9C00 EQU %00001000 ; BG Tile Map Display Select
DEF LCDCF_OBJ8 EQU %00000000 ; OBJ Construction
DEF LCDCF_OBJ16 EQU %00000100 ; OBJ Construction
DEF LCDCF_OBJOFF EQU %00000000 ; OBJ Display
DEF LCDCF_OBJON EQU %00000010 ; OBJ Display
DEF LCDCF_BGOFF EQU %00000000 ; BG Display
DEF LCDCF_BGON EQU %00000001 ; BG Display
endc
; "Window Character Data Select" follows BG
; --
; -- STAT ($FF41)
; -- LCDC Status (R/W)
; --
if def(TARGET_MEGADUCK)
DEF rSTAT EQU $FF11
else
DEF rSTAT EQU $FF41
endc
DEF STATF_LYC EQU %01000000 ; LYC=LY Coincidence (Selectable)
DEF STATF_MODE10 EQU %00100000 ; Mode 10
DEF STATF_MODE01 EQU %00010000 ; Mode 01 (V-Blank)
DEF STATF_MODE00 EQU %00001000 ; Mode 00 (H-Blank)
DEF STATF_LYCF EQU %00000100 ; Coincidence Flag
DEF STATF_HBL EQU %00000000 ; H-Blank
DEF STATF_VBL EQU %00000001 ; V-Blank
DEF STATF_OAM EQU %00000010 ; OAM-RAM is used by system
DEF STATF_LCD EQU %00000011 ; Both OAM and VRAM used by system
DEF STATF_BUSY EQU %00000010 ; When set, VRAM access is unsafe
; --
; -- SCY ($FF42)
; -- Scroll Y (R/W)
; --
if def(TARGET_MEGADUCK)
DEF rSCY EQU $FF12
else
DEF rSCY EQU $FF42
endc
; --
; -- SCX ($FF43)
; -- Scroll X (R/W)
; --
if def(TARGET_MEGADUCK)
DEF rSCX EQU $FF13
else
DEF rSCX EQU $FF43
endc
; --
; -- LY ($FF44)
; -- LCDC Y-Coordinate (R)
; --
; -- Values range from 0->153. 144->153 is the VBlank period.
; --
if def(TARGET_MEGADUCK)
DEF rLY EQU $FF18
else
DEF rLY EQU $FF44
endc
; --
; -- LYC ($FF45)
; -- LY Compare (R/W)
; --
; -- When LY==LYC, STATF_LYCF will be set in STAT
; --
if def(TARGET_MEGADUCK)
DEF rLYC EQU $FF19
else
DEF rLYC EQU $FF45
endc
; --
; -- DMA ($FF46)
; -- DMA Transfer and Start Address (W)
; --
if def(TARGET_MEGADUCK)
DEF rDMA EQU $FF1A
else
DEF rDMA EQU $FF46
endc
; --
; -- BGP ($FF47)
; -- BG Palette Data (W)
; --
; -- Bit 7-6 - Intensity for %11
; -- Bit 5-4 - Intensity for %10
; -- Bit 3-2 - Intensity for %01
; -- Bit 1-0 - Intensity for %00
; --
if def(TARGET_MEGADUCK)
DEF rBGP EQU $FF1B
else
DEF rBGP EQU $FF47
endc
; --
; -- OBP0 ($FF48)
; -- Object Palette 0 Data (W)
; --
; -- See BGP for info
; --
if def(TARGET_MEGADUCK)
DEF rOBP0 EQU $FF14
else
DEF rOBP0 EQU $FF48
endc
; --
; -- OBP1 ($FF49)
; -- Object Palette 1 Data (W)
; --
; -- See BGP for info
; --
if def(TARGET_MEGADUCK)
DEF rOBP1 EQU $FF15
else
DEF rOBP1 EQU $FF49
endc
; --
; -- WY ($FF4A)
; -- Window Y Position (R/W)
; --
; -- 0 <= WY <= 143
; -- When WY = 0, the window is displayed from the top edge of the LCD screen.
; --
if def(TARGET_MEGADUCK)
DEF rWY EQU $FF16
else
DEF rWY EQU $FF4A
endc
; --
; -- WX ($FF4B)
; -- Window X Position (R/W)
; --
; -- 7 <= WX <= 166
; -- When WX = 7, the window is displayed from the left edge of the LCD screen.
; -- Values of 0-6 and 166 are unreliable due to hardware bugs.
; --
if def(TARGET_MEGADUCK)
DEF rWX EQU $FF17
else
DEF rWX EQU $FF4B
endc
; --
; -- SPEED ($FF4D)
; -- Select CPU Speed (R/W)
; --
DEF rKEY1 EQU $FF4D
DEF rSPD EQU rKEY1
DEF KEY1F_DBLSPEED EQU %10000000 ; 0=Normal Speed, 1=Double Speed (R)
DEF KEY1F_PREPARE EQU %00000001 ; 0=No, 1=Prepare (R/W)
; --
; -- VBK ($FF4F)
; -- Select Video RAM Bank (R/W)
; --
; -- Bit 0 - Bank Specification (0: Specify Bank 0; 1: Specify Bank 1)
; --
DEF rVBK EQU $FF4F
; --
; -- HDMA1 ($FF51)
; -- High byte for Horizontal Blanking/General Purpose DMA source address (W)
; -- CGB Mode Only
; --
DEF rHDMA1 EQU $FF51
; --
; -- HDMA2 ($FF52)
; -- Low byte for Horizontal Blanking/General Purpose DMA source address (W)
; -- CGB Mode Only
; --
DEF rHDMA2 EQU $FF52
; --
; -- HDMA3 ($FF53)
; -- High byte for Horizontal Blanking/General Purpose DMA destination address (W)
; -- CGB Mode Only
; --
DEF rHDMA3 EQU $FF53
; --
; -- HDMA4 ($FF54)
; -- Low byte for Horizontal Blanking/General Purpose DMA destination address (W)
; -- CGB Mode Only
; --
DEF rHDMA4 EQU $FF54
; --
; -- HDMA5 ($FF55)
; -- Transfer length (in tiles minus 1)/mode/start for Horizontal Blanking, General Purpose DMA (R/W)
; -- CGB Mode Only
; --
DEF rHDMA5 EQU $FF55
DEF HDMA5F_MODE_GP EQU %00000000 ; General Purpose DMA (W)
DEF HDMA5F_MODE_HBL EQU %10000000 ; HBlank DMA (W)
; -- Once DMA has started, use HDMA5F_BUSY to check when the transfer is complete
DEF HDMA5F_BUSY EQU %10000000 ; 0=Busy (DMA still in progress), 1=Transfer complete (R)
; --
; -- RP ($FF56)
; -- Infrared Communications Port (R/W)
; -- CGB Mode Only
; --
DEF rRP EQU $FF56
DEF RPF_ENREAD EQU %11000000
DEF RPF_DATAIN EQU %00000010 ; 0=Receiving IR Signal, 1=Normal
DEF RPF_WRITE_HI EQU %00000001
DEF RPF_WRITE_LO EQU %00000000
; --
; -- BCPS ($FF68)
; -- Background Color Palette Specification (R/W)
; --
DEF rBCPS EQU $FF68
DEF BCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing)
; --
; -- BCPD ($FF69)
; -- Background Color Palette Data (R/W)
; --
DEF rBCPD EQU $FF69
; --
; -- OCPS ($FF6A)
; -- Object Color Palette Specification (R/W)
; --
DEF rOCPS EQU $FF6A
DEF OCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing)
; --
; -- OCPD ($FF6B)
; -- Object Color Palette Data (R/W)
; --
DEF rOCPD EQU $FF6B
; --
; -- SMBK/SVBK ($FF70)
; -- Select Main RAM Bank (R/W)
; --
; -- Bit 2-0 - Bank Specification (0,1: Specify Bank 1; 2-7: Specify Banks 2-7)
; --
DEF rSVBK EQU $FF70
DEF rSMBK EQU rSVBK
; --
; -- PCM12 ($FF76)
; -- Sound channel 1&2 PCM amplitude (R)
; --
; -- Bit 7-4 - Copy of sound channel 2's PCM amplitude
; -- Bit 3-0 - Copy of sound channel 1's PCM amplitude
; --
DEF rPCM12 EQU $FF76
; --
; -- PCM34 ($FF77)
; -- Sound channel 3&4 PCM amplitude (R)
; --
; -- Bit 7-4 - Copy of sound channel 4's PCM amplitude
; -- Bit 3-0 - Copy of sound channel 3's PCM amplitude
; --
DEF rPCM34 EQU $FF77
; --
; -- IE ($FFFF)
; -- Interrupt Enable (R/W)
; --
DEF rIE EQU $FFFF
DEF IEF_HILO EQU %00010000 ; Transition from High to Low of Pin number P10-P13
DEF IEF_SERIAL EQU %00001000 ; Serial I/O transfer end
DEF IEF_TIMER EQU %00000100 ; Timer Overflow
DEF IEF_STAT EQU %00000010 ; STAT
DEF IEF_VBLANK EQU %00000001 ; V-Blank
;***************************************************************************
;*
;* Flags common to multiple sound channels
;*
;***************************************************************************
; --
; -- Square wave duty cycle
; --
; -- Can be used with AUD1LEN and AUD2LEN
; -- See AUD1LEN for more info
; --
DEF AUDLEN_DUTY_12_5 EQU %00000000 ; 12.5%
DEF AUDLEN_DUTY_25 EQU %01000000 ; 25%
DEF AUDLEN_DUTY_50 EQU %10000000 ; 50%
DEF AUDLEN_DUTY_75 EQU %11000000 ; 75%
; --
; -- Audio envelope flags
; --
; -- Can be used with AUD1ENV, AUD2ENV, AUD4ENV
; -- See AUD1ENV for more info
; --
DEF AUDENV_UP EQU %00001000
DEF AUDENV_DOWN EQU %00000000
; --
; -- Audio trigger flags
; --
; -- Can be used with AUD1HIGH, AUD2HIGH, AUD3HIGH
; -- See AUD1HIGH for more info
; --
DEF AUDHIGH_RESTART EQU %10000000
DEF AUDHIGH_LENGTH_ON EQU %01000000
DEF AUDHIGH_LENGTH_OFF EQU %00000000
;***************************************************************************
;*
;* CPU values on bootup (a=type, b=qualifier)
;*
;***************************************************************************
DEF BOOTUP_A_DMG EQU $01 ; Dot Matrix Game
DEF BOOTUP_A_CGB EQU $11 ; Color GameBoy
DEF BOOTUP_A_MGB EQU $FF ; Mini GameBoy (Pocket GameBoy)
; if a=BOOTUP_A_CGB, bit 0 in b can be checked to determine if real CGB or
; other system running in GBC mode
DEF BOOTUP_B_CGB EQU %00000000
DEF BOOTUP_B_AGB EQU %00000001 ; GBA, GBA SP, Game Boy Player, or New GBA SP
;***************************************************************************
;*
;* Cart related
;*
;***************************************************************************
; $0143 Color GameBoy compatibility code
DEF CART_COMPATIBLE_DMG EQU $00
DEF CART_COMPATIBLE_DMG_GBC EQU $80
DEF CART_COMPATIBLE_GBC EQU $C0
; $0146 GameBoy/Super GameBoy indicator
DEF CART_INDICATOR_GB EQU $00
DEF CART_INDICATOR_SGB EQU $03
; $0147 Cartridge type
DEF CART_ROM EQU $00
DEF CART_ROM_MBC1 EQU $01
DEF CART_ROM_MBC1_RAM EQU $02
DEF CART_ROM_MBC1_RAM_BAT EQU $03
DEF CART_ROM_MBC2 EQU $05
DEF CART_ROM_MBC2_BAT EQU $06
DEF CART_ROM_RAM EQU $08
DEF CART_ROM_RAM_BAT EQU $09
DEF CART_ROM_MMM01 EQU $0B
DEF CART_ROM_MMM01_RAM EQU $0C
DEF CART_ROM_MMM01_RAM_BAT EQU $0D
DEF CART_ROM_MBC3_BAT_RTC EQU $0F
DEF CART_ROM_MBC3_RAM_BAT_RTC EQU $10
DEF CART_ROM_MBC3 EQU $11
DEF CART_ROM_MBC3_RAM EQU $12
DEF CART_ROM_MBC3_RAM_BAT EQU $13
DEF CART_ROM_MBC5 EQU $19
DEF CART_ROM_MBC5_BAT EQU $1A
DEF CART_ROM_MBC5_RAM_BAT EQU $1B
DEF CART_ROM_MBC5_RUMBLE EQU $1C
DEF CART_ROM_MBC5_RAM_RUMBLE EQU $1D
DEF CART_ROM_MBC5_RAM_BAT_RUMBLE EQU $1E
DEF CART_ROM_MBC7_RAM_BAT_GYRO EQU $22
DEF CART_ROM_POCKET_CAMERA EQU $FC
DEF CART_ROM_BANDAI_TAMA5 EQU $FD
DEF CART_ROM_HUDSON_HUC3 EQU $FE
DEF CART_ROM_HUDSON_HUC1 EQU $FF
; $0148 ROM size
; these are kilobytes
DEF CART_ROM_32KB EQU $00 ; 2 banks
DEF CART_ROM_64KB EQU $01 ; 4 banks
DEF CART_ROM_128KB EQU $02 ; 8 banks
DEF CART_ROM_256KB EQU $03 ; 16 banks
DEF CART_ROM_512KB EQU $04 ; 32 banks
DEF CART_ROM_1024KB EQU $05 ; 64 banks
DEF CART_ROM_2048KB EQU $06 ; 128 banks
DEF CART_ROM_4096KB EQU $07 ; 256 banks
DEF CART_ROM_8192KB EQU $08 ; 512 banks
DEF CART_ROM_1152KB EQU $52 ; 72 banks
DEF CART_ROM_1280KB EQU $53 ; 80 banks
DEF CART_ROM_1536KB EQU $54 ; 96 banks
; $0149 SRAM size
; these are kilobytes
DEF CART_SRAM_NONE EQU 0
DEF CART_SRAM_2KB EQU 1 ; 1 incomplete bank
DEF CART_SRAM_8KB EQU 2 ; 1 bank
DEF CART_SRAM_32KB EQU 3 ; 4 banks
DEF CART_SRAM_128KB EQU 4 ; 16 banks
DEF CART_SRAM_ENABLE EQU $0A
DEF CART_SRAM_DISABLE EQU $00
; $014A Destination code
DEF CART_DEST_JAPANESE EQU $00
DEF CART_DEST_NON_JAPANESE EQU $01
;***************************************************************************
;*
;* Keypad related
;*
;***************************************************************************
DEF PADF_DOWN EQU $80
DEF PADF_UP EQU $40
DEF PADF_LEFT EQU $20
DEF PADF_RIGHT EQU $10