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First working SIMD version with basic AVX2 support (runtime use is decided at compile time)
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‎Makefile.am

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@@ -86,7 +86,9 @@ bin_md5_birthdaysearch_SOURCES=\
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src/md5birthdaysearch/main.cpp \
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src/md5birthdaysearch/main.hpp \
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src/md5birthdaysearch/storage.cpp \
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src/md5birthdaysearch/storage.hpp
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src/md5birthdaysearch/storage.hpp \
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src/md5birthdaysearch/simd_avx256.cpp
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if HAVE_CUDA
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bin_md5_birthdaysearch_SOURCES+=\
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src/md5birthdaysearch/cuda_md5.cu

‎configure.ac

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@@ -35,6 +35,10 @@ AC_TYPE_UINT8_T
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AS_IF([test "x$cross_compiling" != "xyes" && test "x$usedefaultcxxflags" = "xyes" ],
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[AX_CHECK_COMPILE_FLAG([-march=native], [CXXFLAGS="$CXXFLAGS -march=native"], [])])
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# hide the masses of deprecated warnings because of the old Boost version
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AX_CHECK_COMPILE_FLAG([-Wno-deprecated-declarations], [CXXFLAGS="$CXXFLAGS -Wno-deprecated-declarations"], [])
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AX_CHECK_COMPILE_FLAG([-Wno-deprecated], [CXXFLAGS="$CXXFLAGS -Wno-deprecated"], [])
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AX_PTHREAD()
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LIBS="$PTHREAD_LIBS $LIBS"
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CXXFLAGS="$CXXFLAGS $PTHREAD_CFLAGS"
@@ -53,6 +57,9 @@ CPPFLAGS="$BOOST_CPPFLAGS $CPPFLAGS"
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LDFLAGS="$BOOST_LDFLAGS $LDFLAGS"
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LIBS="$BOOST_FILESYSTEM_LIB $BOOST_IOSTREAMS_LIB $BOOST_PROGRAM_OPTIONS_LIB $BOOST_SERIALIZATION_LIB $BOOST_SYSTEM_LIB $BOOST_THREAD_LIB $LIBS"
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AX_EXT
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CXXFLAGS="$CXXFLAGS $SIMD_FLAGS"
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AX_CUDA
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AC_CONFIG_FILES([

‎lib/hashclash/simd/simd_avx256.h

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@@ -0,0 +1,110 @@
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/***
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* Copyright 2017 Marc Stevens <marc@marc-stevens.nl>, Dan Shumow (danshu@microsoft.com)
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* Distributed under the MIT Software License.
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* See accompanying file LICENSE.txt or copy at
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* https://opensource.org/licenses/MIT
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***/
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/*
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* this header defines SIMD MACROS for avx256 intrinsics
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* used to generate avx256 code from generic SIMD code (sha1_simd.cinc, ubc_check_simd.cinc)
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*/
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#ifndef SIMD_AVX256_HEADER
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#define SIMD_AVX256_HEADER
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#ifdef HASHCLASH_HAVE_AVX2
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/* requires AVX2 not just AVX */
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#define SIMD_VERSION avx256
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#define SIMD_VECSIZE 8
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#ifdef __GNUC__
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/* TODO */
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#include <immintrin.h>
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#define SIMD_WORD __m256i
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#define SIMD_ZERO _mm256_setzero_si256()
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#define SIMD_WTOV(l) _mm256_set1_epi32(l)
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#define SIMD_ADD_VV(l,r) _mm256_add_epi32(l,r)
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#define SIMD_ADD_VW(l,r) _mm256_add_epi32(l, _mm256_set1_epi32(r))
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#define SIMD_SUB_VV(l,r) _mm256_sub_epi32(l,r)
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#define SIMD_SUB_VW(l,r) _mm256_sub_epi32(l, _mm256_set1_epi32(r))
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#define SIMD_AND_VV(l,r) _mm256_and_si256(l,r)
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#define SIMD_AND_VW(l,r) _mm256_and_si256(l, _mm256_set1_epi32(r))
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#define SIMD_ANDNOT_VV(l,r) _mm256_andnot_si256(l,r)
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#define SIMD_ANDNOT_VW(l,r) _mm256_andnot_si256(l, _mm256_set1_epi32(r))
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#define SIMD_ANDNOT_WV(l,r) _mm256_andnot_si256(_mm256_set1_epi32(l), r)
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#define SIMD_OR_VV(l,r) _mm256_or_si256(l,r)
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#define SIMD_OR_VW(l,r) _mm256_or_si256(l, _mm256_set1_epi32(r))
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#define SIMD_XOR_VV(l,r) _mm256_xor_si256(l,r)
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#define SIMD_XOR_VW(l,r) _mm256_xor_si256(l, _mm256_set1_epi32(r))
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/*#define SIMD_NOT_V(l) _mm256_andnot_si256(l,l)*/
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#define SIMD_SHL_V(l,i) _mm256_slli_epi32(l,i)
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#define SIMD_SHR_V(l,i) _mm256_srli_epi32(l,i)
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/*#define SIMD_ROL_V(l,i) _mm256_rol_epi32(l,i)*/
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/*#define SIMD_ROR_V(l,i) _mm256_ror_epi32(l,i)*/
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#define SIMD_EQ_VV(a,b) _mm256_cmpeq_epi32(a,b)
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#define SIMD_MIN_VV(a,b) _mm256_min_epu32(a,b)
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#define SIMD_SEL_VWW(m,a,b) SIMD_OR_VV( SIMD_AND_VW(m,a), SIMD_ANDNOT_VW(m,b) )
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#define SIMD_SEL_VVV(m,a,b) SIMD_OR_VV( SIMD_AND_VV(m,a), SIMD_ANDNOT_VV(m,b) )
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#define SIMD_CLEANUP
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#else /* __GNUC__ */
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/* VISUAL STUDIO */
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#include <immintrin.h>
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#define SIMD_WORD __m256i
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#define SIMD_ZERO _mm256_setzero_si256()
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#define SIMD_WTOV(l) _mm256_set1_epi32(l)
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#define SIMD_ADD_VV(l,r) _mm256_add_epi32(l,r)
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#define SIMD_ADD_VW(l,r) _mm256_add_epi32(l, _mm256_set1_epi32(r))
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#define SIMD_SUB_VV(l,r) _mm256_sub_epi32(l,r)
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#define SIMD_SUB_VW(l,r) _mm256_sub_epi32(l, _mm256_set1_epi32(r))
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#define SIMD_AND_VV(l,r) _mm256_and_si256(l,r)
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#define SIMD_AND_VW(l,r) _mm256_and_si256(l, _mm256_set1_epi32(r))
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#define SIMD_ANDNOT_VV(l,r) _mm256_andnot_si256(l,r)
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#define SIMD_ANDNOT_VW(l,r) _mm256_andnot_si256(l, _mm256_set1_epi32(r))
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#define SIMD_ANDNOT_WV(l,r) _mm256_andnot_si256(_mm256_set1_epi32(l), r)
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#define SIMD_OR_VV(l,r) _mm256_or_si256(l,r)
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#define SIMD_OR_VW(l,r) _mm256_or_si256(l, _mm256_set1_epi32(r))
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#define SIMD_XOR_VV(l,r) _mm256_xor_si256(l,r)
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#define SIMD_XOR_VW(l,r) _mm256_xor_si256(l, _mm256_set1_epi32(r))
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/*#define SIMD_NOT_V(l) _mm256_andnot_si256(l,l)*/
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#define SIMD_SHL_V(l,i) _mm256_slli_epi32(l,i)
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#define SIMD_SHR_V(l,i) _mm256_srli_epi32(l,i)
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/*#define SIMD_ROL_V(l,i) _mm256_rol_epi32(l,i)*/
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/*#define SIMD_ROR_V(l,i) _mm256_ror_epi32(l,i)*/
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#define SIMD_EQ_VV(a,b) _mm256_cmpeq_epi32(a,b)
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#define SIMD_MIN_VV(a,b) _mm256_min_epu32(a,b)
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#define SIMD_SEL_VWW(m,a,b) SIMD_OR_VV( SIMD_AND_VW(m,a), SIMD_ANDNOT_VW(m,b) )
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#define SIMD_SEL_VVV(m,a,b) SIMD_OR_VV( SIMD_AND_VV(m,a), SIMD_ANDNOT_VV(m,b) )
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#define SIMD_CLEANUP
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#endif /* __GNUC__ */
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/* these are general definitions for lacking SIMD operations */
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#ifndef SIMD_NOT_V
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#define SIMD_NOT_V(l) SIMD_XOR_VW(l,0xFFFFFFFF)
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#endif
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#ifndef SIMD_NEG_V
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#define SIMD_NEG_V(l) SIMD_SUB_VV(SIMD_ZERO,l)
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#endif
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#ifndef SIMD_ROL_V
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#define SIMD_ROL_V(l,i) SIMD_OR_VV(SIMD_SHL_V(l,i),SIMD_SHR_V(l,32-i))
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#define SIMD_ROR_V(l,i) SIMD_OR_VV(SIMD_SHR_V(l,i),SIMD_SHL_V(l,32-i))
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#endif
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#endif /* HASHCLASH_HAVE_AVX2 */
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#endif /* SIMD_AVX256_HEADER */

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