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| 1 | +* Freescale IOMUX Controller (IOMUXC) for i.MX |
| 2 | + |
| 3 | +The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC |
| 4 | +to share one PAD to several functional blocks. The sharing is done by |
| 5 | +multiplexing the PAD input/output signals. For each PAD there are up to |
| 6 | +8 muxing options (called ALT modes). Since different modules require |
| 7 | +different PAD settings (like pull up, keeper, etc) the IOMUXC controls |
| 8 | +also the PAD settings parameters. |
| 9 | + |
| 10 | +Please refer to pinctrl-bindings.txt in this directory for details of the |
| 11 | +common pinctrl bindings used by client devices, including the meaning of the |
| 12 | +phrase "pin configuration node". |
| 13 | + |
| 14 | +Freescale IMX pin configuration node is a node of a group of pins which can be |
| 15 | +used for a specific device or function. This node represents both mux and config |
| 16 | +of the pins in that group. The 'mux' selects the function mode(also named mux |
| 17 | +mode) this pin can work on and the 'config' configures various pad settings |
| 18 | +such as pull-up, open drain, drive strength, etc. |
| 19 | + |
| 20 | +Required properties for iomux controller: |
| 21 | +- compatible: "fsl,<soc>-iomuxc" |
| 22 | + Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs. |
| 23 | + |
| 24 | +Required properties for pin configuration node: |
| 25 | +- fsl,pins: two integers array, represents a group of pins mux and config |
| 26 | + setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a |
| 27 | + pin working on a specific function, CONFIG is the pad setting value like |
| 28 | + pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid |
| 29 | + pins and functions of each SoC. |
| 30 | + |
| 31 | +Bits used for CONFIG: |
| 32 | +NO_PAD_CTL(1 << 31): indicate this pin does not need config. |
| 33 | + |
| 34 | +SION(1 << 30): Software Input On Field. |
| 35 | +Force the selected mux mode input path no matter of MUX_MODE functionality. |
| 36 | +By default the input path is determined by functionality of the selected |
| 37 | +mux mode (regular). |
| 38 | + |
| 39 | +Other bits are used for PAD setting. |
| 40 | +Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part |
| 41 | +of bits definitions. |
| 42 | + |
| 43 | +NOTE: |
| 44 | +Some requirements for using fsl,imx-pinctrl binding: |
| 45 | +1. We have pin function node defined under iomux controller node to represent |
| 46 | + what pinmux functions this SoC supports. |
| 47 | +2. The pin configuration node intends to work on a specific function should |
| 48 | + to be defined under that specific function node. |
| 49 | + The function node's name should represent well about what function |
| 50 | + this group of pins in this pin configuration node are working on. |
| 51 | +3. The driver can use the function node's name and pin configuration node's |
| 52 | + name describe the pin function and group hierarchy. |
| 53 | + For example, Linux IMX pinctrl driver takes the function node's name |
| 54 | + as the function name and pin configuration node's name as group name to |
| 55 | + create the map table. |
| 56 | +4. Each pin configuration node should have a phandle, devices can set pins |
| 57 | + configurations by referring to the phandle of that pin configuration node. |
| 58 | + |
| 59 | +Examples: |
| 60 | +usdhc@0219c000 { /* uSDHC4 */ |
| 61 | + fsl,card-wired; |
| 62 | + vmmc-supply = <®_3p3v>; |
| 63 | + status = "okay"; |
| 64 | + pinctrl-names = "default"; |
| 65 | + pinctrl-0 = <&pinctrl_usdhc4_1>; |
| 66 | +}; |
| 67 | + |
| 68 | +iomuxc@020e0000 { |
| 69 | + compatible = "fsl,imx6q-iomuxc"; |
| 70 | + reg = <0x020e0000 0x4000>; |
| 71 | + |
| 72 | + /* shared pinctrl settings */ |
| 73 | + usdhc4 { |
| 74 | + pinctrl_usdhc4_1: usdhc4grp-1 { |
| 75 | + fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ |
| 76 | + 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ |
| 77 | + 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ |
| 78 | + 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ |
| 79 | + 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ |
| 80 | + 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ |
| 81 | + 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ |
| 82 | + 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ |
| 83 | + 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ |
| 84 | + 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ |
| 85 | + }; |
| 86 | + }; |
| 87 | + .... |
| 88 | +}; |
| 89 | +Refer to the IOMUXC controller chapter in imx6q datasheet, |
| 90 | +0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, |
| 91 | +80Ohm driver strength and Fast Slew Rate. |
| 92 | +User should refer to each SoC spec to set the correct value. |
| 93 | + |
| 94 | +TODO: when dtc macro support is available, we can change above raw data |
| 95 | +to dt macro which can get better readability in dts file. |
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