UART output garbled when building Litex SoC for CrossLinkNX with Radiant 2024.2

[polymerizedsage]

I am developing a Litex-based SoC my project girlvoice. I have been using Radiant 2023.2 for most of my development but recently updated to Radiant 2024.2. When building with the older version of Radiant the SoC boots and I get coherent UART output, however after updating to the newer toolchain, the UART output is garbled with invalid characters.

The design uses a custom PCB with a Lattice CrossLinkNX-17 72-pin QFN speed grade 8 device. I am using the latest version of Litex distributed on Pypi, which I believe is 2023.12. If it would be helpful I can post an example of the garbled boot output of the SoC

[enjoy-digital]

Hi @polymerizedsage,

yes please feel free to share expected output and garbled ouptut. Have you tried to look at the UART in both case with a scope to verify that baudrate is OK? One possible issue could be that, if using a PLL in the design, the generated frequency is no longer correct. This could also be worth adding a margin=0 to the create_clkout method and verify the generated frequency with a scope (direct or divider by logic).

@trabucayre: Do you remember the version of Radiant we've been using on recent Lattice CrossLinkNX projects?

[trabucayre]

@enjoy-digital we have used radiant 2023.2