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media: imx-jpeg: Add V4L2 driver for i.MX8 JPEG Encoder/Decoder
V4L2 driver for the JPEG encoder/decoder from i.MX8QXP/i.MX8QM application processors. The multi-planar buffers API is used. Baseline and extended sequential jpeg decoding is supported. Progressive jpeg decoding is not supported by the IP. Supports encode and decode of various formats: YUV444, YUV422, YUV420, RGB, ARGB, Gray YUV420 is the only multi-planar format supported. Minimum resolution is 64 x 64, maximum 8192 x 8192. The alignment requirements for the resolution depend on the format, multiple of 16 resolutions should work for all formats. v4l2-compliance tests are passing, including the streaming tests, "v4l2-compliance -s" [hverkuil: fix kernel-doc typos] Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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‎drivers/media/platform/Kconfig

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@@ -253,6 +253,8 @@ config VIDEO_IMX_PXP
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The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
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color space conversion, and rotation.
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source "drivers/media/platform/imx-jpeg/Kconfig"
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config VIDEO_MEDIATEK_JPEG
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tristate "Mediatek JPEG Codec driver"
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depends on MTK_IOMMU_V1 || MTK_IOMMU || COMPILE_TEST

‎drivers/media/platform/Makefile

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@@ -21,6 +21,7 @@ obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o
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obj-$(CONFIG_VIDEO_CODA) += coda/
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obj-$(CONFIG_VIDEO_IMX_PXP) += imx-pxp.o
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obj-$(CONFIG_VIDEO_IMX8_JPEG) += imx-jpeg/
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obj-$(CONFIG_VIDEO_MEM2MEM_DEINTERLACE) += m2m-deinterlace.o
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‎drivers/media/platform/imx-jpeg/Kconfig

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# SPDX-License-Identifier: GPL-2.0
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config VIDEO_IMX8_JPEG
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tristate "IMX8 JPEG Encoder/Decoder"
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depends on VIDEO_DEV && VIDEO_V4L2
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select VIDEOBUF2_DMA_CONTIG
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select V4L2_MEM2MEM_DEV
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select V4L2_JPEG_HELPER
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default m
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help
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This is a video4linux2 driver for the i.MX8 QXP/QM integrated
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JPEG encoder/decoder.

‎drivers/media/platform/imx-jpeg/Makefile

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# SPDX-License-Identifier: GPL-2.0
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mxc-jpeg-encdec-objs := mxc-jpeg-hw.o mxc-jpeg.o
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obj-$(CONFIG_VIDEO_IMX8_JPEG) += mxc-jpeg-encdec.o

‎drivers/media/platform/imx-jpeg/mxc-jpeg-hw.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
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*
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* Copyright 2018-2019 NXP
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*/
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#include <linux/delay.h>
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#include <media/videobuf2-core.h>
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#include "mxc-jpeg-hw.h"
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#define print_wrapper_reg(dev, base_address, reg_offset)\
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internal_print_wrapper_reg(dev, (base_address), #reg_offset,\
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(reg_offset))
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#define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\
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int val;\
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val = readl((base_address) + (reg_offset));\
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dev_dbg(dev, "Wrapper reg %s = 0x%x\n", reg_name, val);\
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}
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void print_descriptor_info(struct device *dev, struct mxc_jpeg_desc *desc)
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{
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dev_dbg(dev, " MXC JPEG NEXT_DESCPT_PTR 0x%x\n",
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desc->next_descpt_ptr);
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dev_dbg(dev, " MXC JPEG BUF_BASE0 0x%x\n", desc->buf_base0);
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dev_dbg(dev, " MXC JPEG BUF_BASE1 0x%x\n", desc->buf_base1);
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dev_dbg(dev, " MXC JPEG LINE_PITCH %d\n", desc->line_pitch);
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dev_dbg(dev, " MXC JPEG STM_BUFBASE 0x%x\n", desc->stm_bufbase);
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dev_dbg(dev, " MXC JPEG STM_BUFSIZE %d\n", desc->stm_bufsize);
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dev_dbg(dev, " MXC JPEG IMGSIZE %x (%d x %d)\n", desc->imgsize,
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desc->imgsize >> 16, desc->imgsize & 0xFFFF);
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dev_dbg(dev, " MXC JPEG STM_CTRL 0x%x\n", desc->stm_ctrl);
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}
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void print_cast_status(struct device *dev, void __iomem *reg,
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unsigned int mode)
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{
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dev_dbg(dev, "CAST IP status regs:\n");
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print_wrapper_reg(dev, reg, CAST_STATUS0);
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print_wrapper_reg(dev, reg, CAST_STATUS1);
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print_wrapper_reg(dev, reg, CAST_STATUS2);
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print_wrapper_reg(dev, reg, CAST_STATUS3);
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print_wrapper_reg(dev, reg, CAST_STATUS4);
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print_wrapper_reg(dev, reg, CAST_STATUS5);
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print_wrapper_reg(dev, reg, CAST_STATUS6);
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print_wrapper_reg(dev, reg, CAST_STATUS7);
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print_wrapper_reg(dev, reg, CAST_STATUS8);
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print_wrapper_reg(dev, reg, CAST_STATUS9);
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print_wrapper_reg(dev, reg, CAST_STATUS10);
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print_wrapper_reg(dev, reg, CAST_STATUS11);
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print_wrapper_reg(dev, reg, CAST_STATUS12);
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print_wrapper_reg(dev, reg, CAST_STATUS13);
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if (mode == MXC_JPEG_DECODE)
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return;
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print_wrapper_reg(dev, reg, CAST_STATUS14);
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print_wrapper_reg(dev, reg, CAST_STATUS15);
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print_wrapper_reg(dev, reg, CAST_STATUS16);
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print_wrapper_reg(dev, reg, CAST_STATUS17);
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print_wrapper_reg(dev, reg, CAST_STATUS18);
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print_wrapper_reg(dev, reg, CAST_STATUS19);
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}
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void print_wrapper_info(struct device *dev, void __iomem *reg)
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{
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dev_dbg(dev, "Wrapper regs:\n");
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print_wrapper_reg(dev, reg, GLB_CTRL);
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print_wrapper_reg(dev, reg, COM_STATUS);
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print_wrapper_reg(dev, reg, BUF_BASE0);
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print_wrapper_reg(dev, reg, BUF_BASE1);
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print_wrapper_reg(dev, reg, LINE_PITCH);
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print_wrapper_reg(dev, reg, STM_BUFBASE);
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print_wrapper_reg(dev, reg, STM_BUFSIZE);
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print_wrapper_reg(dev, reg, IMGSIZE);
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print_wrapper_reg(dev, reg, STM_CTRL);
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}
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void mxc_jpeg_enable_irq(void __iomem *reg, int slot)
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{
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writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));
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}
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void mxc_jpeg_sw_reset(void __iomem *reg)
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{
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/*
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* engine soft reset, internal state machine reset
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* this will not reset registers, however, it seems
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* the registers may remain inconsistent with the internal state
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* so, on purpose, at least let GLB_CTRL bits clear after this reset
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*/
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writel(GLB_CTRL_SFT_RST, reg + GLB_CTRL);
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}
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void mxc_jpeg_enc_mode_conf(struct device *dev, void __iomem *reg)
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{
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dev_dbg(dev, "CAST Encoder CONFIG...\n");
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/*
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* "Config_Mode" enabled, "Config_Mode auto clear enabled",
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*/
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writel(0xa0, reg + CAST_MODE);
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/* all markers and segments */
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writel(0x3ff, reg + CAST_CFG_MODE);
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/* quality factor */
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writel(0x4b, reg + CAST_QUALITY);
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}
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void mxc_jpeg_enc_mode_go(struct device *dev, void __iomem *reg)
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{
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dev_dbg(dev, "CAST Encoder GO...\n");
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/*
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* "GO" enabled, "GO bit auto clear" enabled
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*/
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writel(0x140, reg + CAST_MODE);
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}
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void mxc_jpeg_dec_mode_go(struct device *dev, void __iomem *reg)
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{
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dev_dbg(dev, "CAST Decoder GO...\n");
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writel(MXC_DEC_EXIT_IDLE_MODE, reg + CAST_CTRL);
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}
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int mxc_jpeg_enable(void __iomem *reg)
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{
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u32 regval;
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writel(GLB_CTRL_JPG_EN, reg + GLB_CTRL);
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regval = readl(reg);
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return regval;
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}
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void mxc_jpeg_enable_slot(void __iomem *reg, int slot)
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{
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u32 regval;
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regval = readl(reg + GLB_CTRL);
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writel(GLB_CTRL_SLOT_EN(slot) | regval, reg + GLB_CTRL);
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}
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void mxc_jpeg_set_l_endian(void __iomem *reg, int le)
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{
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u32 regval;
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regval = readl(reg + GLB_CTRL);
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regval &= ~GLB_CTRL_L_ENDIAN(1); /* clear */
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writel(GLB_CTRL_L_ENDIAN(le) | regval, reg + GLB_CTRL); /* set */
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}
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void mxc_jpeg_set_bufsize(struct mxc_jpeg_desc *desc, u32 bufsize)
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{
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desc->stm_bufsize = bufsize;
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}
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void mxc_jpeg_set_res(struct mxc_jpeg_desc *desc, u16 w, u16 h)
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{
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desc->imgsize = w << 16 | h;
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}
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void mxc_jpeg_set_line_pitch(struct mxc_jpeg_desc *desc, u32 line_pitch)
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{
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desc->line_pitch = line_pitch;
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}
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void mxc_jpeg_set_desc(u32 desc, void __iomem *reg, int slot)
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{
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writel(desc | MXC_NXT_DESCPT_EN,
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reg + MXC_SLOT_OFFSET(slot, SLOT_NXT_DESCPT_PTR));
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}

‎drivers/media/platform/imx-jpeg/mxc-jpeg-hw.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
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*
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* Copyright 2018-2019 NXP
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*/
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#ifndef _MXC_JPEG_HW_H
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#define _MXC_JPEG_HW_H
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/* JPEG Decoder/Encoder Wrapper Register Map */
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#define GLB_CTRL 0x0
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#define COM_STATUS 0x4
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#define BUF_BASE0 0x14
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#define BUF_BASE1 0x18
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#define LINE_PITCH 0x1C
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#define STM_BUFBASE 0x20
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#define STM_BUFSIZE 0x24
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#define IMGSIZE 0x28
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#define STM_CTRL 0x2C
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/* CAST JPEG-Decoder/Encoder Status Register Map (read-only)*/
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#define CAST_STATUS0 0x100
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#define CAST_STATUS1 0x104
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#define CAST_STATUS2 0x108
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#define CAST_STATUS3 0x10c
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#define CAST_STATUS4 0x110
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#define CAST_STATUS5 0x114
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#define CAST_STATUS6 0x118
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#define CAST_STATUS7 0x11c
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#define CAST_STATUS8 0x120
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#define CAST_STATUS9 0x124
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#define CAST_STATUS10 0x128
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#define CAST_STATUS11 0x12c
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#define CAST_STATUS12 0x130
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#define CAST_STATUS13 0x134
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/* the following are for encoder only */
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#define CAST_STATUS14 0x138
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#define CAST_STATUS15 0x13c
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#define CAST_STATUS16 0x140
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#define CAST_STATUS17 0x144
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#define CAST_STATUS18 0x148
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#define CAST_STATUS19 0x14c
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/* CAST JPEG-Decoder Control Register Map (write-only) */
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#define CAST_CTRL CAST_STATUS13
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/* CAST JPEG-Encoder Control Register Map (write-only) */
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#define CAST_MODE CAST_STATUS0
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#define CAST_CFG_MODE CAST_STATUS1
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#define CAST_QUALITY CAST_STATUS2
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#define CAST_RSVD CAST_STATUS3
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#define CAST_REC_REGS_SEL CAST_STATUS4
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#define CAST_LUMTH CAST_STATUS5
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#define CAST_CHRTH CAST_STATUS6
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#define CAST_NOMFRSIZE_LO CAST_STATUS7
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#define CAST_NOMFRSIZE_HI CAST_STATUS8
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#define CAST_OFBSIZE_LO CAST_STATUS9
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#define CAST_OFBSIZE_HI CAST_STATUS10
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#define MXC_MAX_SLOTS 1 /* TODO use all 4 slots*/
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/* JPEG-Decoder Wrapper Slot Registers 0..3 */
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#define SLOT_BASE 0x10000
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#define SLOT_STATUS 0x0
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#define SLOT_IRQ_EN 0x4
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#define SLOT_BUF_PTR 0x8
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#define SLOT_CUR_DESCPT_PTR 0xC
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#define SLOT_NXT_DESCPT_PTR 0x10
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#define MXC_SLOT_OFFSET(slot, offset) ((SLOT_BASE * ((slot) + 1)) + (offset))
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/* GLB_CTRL fields */
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#define GLB_CTRL_JPG_EN 0x1
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#define GLB_CTRL_SFT_RST (0x1 << 1)
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#define GLB_CTRL_DEC_GO (0x1 << 2)
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#define GLB_CTRL_L_ENDIAN(le) ((le) << 3)
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#define GLB_CTRL_SLOT_EN(slot) (0x1 << ((slot) + 4))
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/* COM_STAUS fields */
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#define COM_STATUS_DEC_ONGOING(r) (((r) & (1 << 31)) >> 31)
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#define COM_STATUS_CUR_SLOT(r) (((r) & (0x3 << 29)) >> 29)
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/* STM_CTRL fields */
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#define STM_CTRL_PIXEL_PRECISION (0x1 << 2)
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#define STM_CTRL_IMAGE_FORMAT(img_fmt) ((img_fmt) << 3)
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#define STM_CTRL_IMAGE_FORMAT_MASK (0xF << 3)
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#define STM_CTRL_BITBUF_PTR_CLR(clr) ((clr) << 7)
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#define STM_CTRL_AUTO_START(go) ((go) << 8)
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#define STM_CTRL_CONFIG_MOD(mod) ((mod) << 9)
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/* SLOT_STATUS fields for slots 0..3 */
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#define SLOT_STATUS_FRMDONE (0x1 << 3)
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#define SLOT_STATUS_ENC_CONFIG_ERR (0x1 << 8)
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/* SLOT_IRQ_EN fields TBD */
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#define MXC_NXT_DESCPT_EN 0x1
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#define MXC_DEC_EXIT_IDLE_MODE 0x4
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/* JPEG-Decoder Wrapper - STM_CTRL Register Fields */
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#define MXC_PIXEL_PRECISION(precision) ((precision) / 8 << 2)
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enum mxc_jpeg_image_format {
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MXC_JPEG_INVALID = -1,
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MXC_JPEG_YUV420 = 0x0, /* 2 Plannar, Y=1st plane UV=2nd plane */
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MXC_JPEG_YUV422 = 0x1, /* 1 Plannar, YUYV sequence */
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MXC_JPEG_RGB = 0x2, /* RGBRGB packed format */
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MXC_JPEG_YUV444 = 0x3, /* 1 Plannar, YUVYUV sequence */
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MXC_JPEG_GRAY = 0x4, /* Y8 or Y12 or Single Component */
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MXC_JPEG_RESERVED = 0x5,
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MXC_JPEG_ARGB = 0x6,
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};
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#include "mxc-jpeg.h"
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void print_descriptor_info(struct device *dev, struct mxc_jpeg_desc *desc);
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void print_cast_status(struct device *dev, void __iomem *reg,
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unsigned int mode);
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void print_wrapper_info(struct device *dev, void __iomem *reg);
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void mxc_jpeg_sw_reset(void __iomem *reg);
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int mxc_jpeg_enable(void __iomem *reg);
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void wait_frmdone(struct device *dev, void __iomem *reg);
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void mxc_jpeg_enc_mode_conf(struct device *dev, void __iomem *reg);
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void mxc_jpeg_enc_mode_go(struct device *dev, void __iomem *reg);
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void mxc_jpeg_dec_mode_go(struct device *dev, void __iomem *reg);
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int mxc_jpeg_get_slot(void __iomem *reg);
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u32 mxc_jpeg_get_offset(void __iomem *reg, int slot);
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void mxc_jpeg_enable_slot(void __iomem *reg, int slot);
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void mxc_jpeg_set_l_endian(void __iomem *reg, int le);
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void mxc_jpeg_enable_irq(void __iomem *reg, int slot);
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int mxc_jpeg_set_input(void __iomem *reg, u32 in_buf, u32 bufsize);
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int mxc_jpeg_set_output(void __iomem *reg, u16 out_pitch, u32 out_buf,
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u16 w, u16 h);
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void mxc_jpeg_set_config_mode(void __iomem *reg, int config_mode);
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int mxc_jpeg_set_params(struct mxc_jpeg_desc *desc, u32 bufsize, u16
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out_pitch, u32 format);
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void mxc_jpeg_set_bufsize(struct mxc_jpeg_desc *desc, u32 bufsize);
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void mxc_jpeg_set_res(struct mxc_jpeg_desc *desc, u16 w, u16 h);
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void mxc_jpeg_set_line_pitch(struct mxc_jpeg_desc *desc, u32 line_pitch);
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void mxc_jpeg_set_desc(u32 desc, void __iomem *reg, int slot);
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void mxc_jpeg_set_regs_from_desc(struct mxc_jpeg_desc *desc,
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void __iomem *reg);
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#endif

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