[SYCL][FPGA][NFC] Tidy up intel_fpga_reg codegen test

Checks for Clang::CodeGenSYCL/intel-fpga-reg.cpp test were autogenerated
to speed up fixing of LIT tests failures after a patch
"[SYCL] Refactor address space handling in CodeGen library (#2864)".

Reorganize test code and tidy up checks to improve readability.

Signed-off-by: Mikhail Lychkov <mikhail.lychkov@intel.com>

Author: mlychkov