Remove the operand promotion for LHS and RHS.

Operand promotion for unaligned matmul cases is leading to dynamic trip
count and forall loop fusion is not taking place by
iree-codegen-gpu-fuse-and-hoist-parallel-loops.

Author: pashu123

compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp

@@ -1346,8 +1346,6 @@ static LogicalResult setContractConfig(IREE::GPU::TargetAttr target,
       attrs.emplace_back(b.getStringAttr("reduction"),
                          b.getI64ArrayAttr(reductionTileSizes));
 
-      // Promote operands to use shared memory for LHS and RHS.
-      IREE::GPU::setPromotedOperandList(context, attrs, {0, 1});
       auto configDict = b.getDictionaryAttr(attrs);
       auto loweringConfig =
           IREE::GPU::LoweringConfigAttr::get(context, configDict);

compiler/src/iree/compiler/Codegen/LLVMGPU/test/config_matvec.mlir

@@ -271,7 +271,7 @@ func.func @not_vmt() {
 //       CHECK: func.func @not_vmt()
 //  CHECK-SAME:     translation_info = #[[$TRANSLATION]]
 //       CHECK:   linalg.generic
-//  CHECK-SAME:       lowering_config = #iree_gpu.lowering_config<{promote_operands = [0, 1], reduction = [0, 0, 8], thread = [1, 128, 0], workgroup = [1, 128, 1]}>
+//  CHECK-SAME:       lowering_config = #iree_gpu.lowering_config<{reduction = [0, 0, 8], thread = [1, 128, 0], workgroup = [1, 128, 1]}>
 
 // -----
 

compiler/src/iree/compiler/Codegen/LLVMGPU/test/gpu_set_num_workgroups.mlir

@@ -59,7 +59,7 @@ func.func @dot_dispatch_1() {
 // CHECK-SAME:     translation_info = #[[TRANSLATION]]
 //      CHECK:   linalg.fill
 //      CHECK:   linalg.matmul
-// CHECK-SAME:       lowering_config = #iree_gpu.lowering_config<{promote_operands = [0, 1], reduction = [0, 0, 4], thread = [2, 1, 0], workgroup = [4, 2, 1]}>
+// CHECK-SAME:       lowering_config = #iree_gpu.lowering_config<{reduction = [0, 0, 4], thread = [2, 1, 0], workgroup = [4, 2, 1]}>
 
 // -----
 
@@ -86,7 +86,7 @@ func.func @unaligned_k() {
 // CHECK-SAME:     translation_info = #[[TRANSLATION]]
 //      CHECK:   linalg.fill
 //      CHECK:   linalg.matmul
-// CHECK-SAME:       lowering_config = #iree_gpu.lowering_config<{promote_operands = [0, 1], reduction = [0, 0, 2], thread = [1, 16, 0], workgroup = [32, 128, 1]}>
+// CHECK-SAME:       lowering_config = #iree_gpu.lowering_config<{reduction = [0, 0, 2], thread = [1, 16, 0], workgroup = [32, 128, 1]}>
 
 // -----
 
@@ -656,7 +656,7 @@ func.func @_main_dispatch_15_generic_512x4x42x42x64_f32() {
 //  CHECK-SAME:    translation_info = #[[TRANSLATION]]
 //       CHECK:  linalg.fill
 //       CHECK:  linalg.generic
-//  CHECK-SAME:     lowering_config = #iree_gpu.lowering_config<{promote_operands = [0, 1], reduction = [0, 0, 0, 0, 32], thread = [1, 1, 1, 16, 0], workgroup = [1, 1, 32, 128, 1]}>
+//  CHECK-SAME:     lowering_config = #iree_gpu.lowering_config<{reduction = [0, 0, 0, 0, 32], thread = [1, 1, 1, 16, 0], workgroup = [1, 1, 32, 128, 1]}>
 
 // -----
 

compiler/src/iree/compiler/Codegen/LLVMGPU/test/nvvm_pipeline_test.mlir

@@ -87,8 +87,8 @@ hal.executable @dot_dispatch_0 {
 //            CHECK:   hal.executable.variant public @cuda
 //        CHECK-NOT:   llvm.store
 //            CHECK:   llvm.br
-//            CHECK:    llvm.load {{.*}} : !llvm.ptr<3> -> vector<32xf32>
-//   CHECK-COUNT-32:    llvm.load {{.*}} : !llvm.ptr<3> -> vector<16xf32>
+//            CHECK:    llvm.load {{.*}} : !llvm.ptr<1> -> vector<32xf32>
+//   CHECK-COUNT-32:    llvm.load {{.*}} : !llvm.ptr<1> -> vector<16xf32>
 //   CHECK-COUNT-32:    llvm.intr.fmuladd({{.*}}) : (vector<16xf32>, vector<16xf32>, vector<16xf32>) -> vector<16xf32>
 //            CHECK:    llvm.store {{.*}} : vector<16xf32>, !llvm.ptr<1>
 

compiler/src/iree/compiler/Codegen/LLVMGPU/test/rocdl_pipeline_test.mlir

@@ -88,8 +88,8 @@ hal.executable @dot_dispatch_0 {
 //         RDNA3:   hal.executable.variant public @rocm
 //       RDNA3-NOT:   llvm.store
 //           RDNA3:   llvm.br
-//   RDNA3-COUNT-1:    llvm.load {{.*}} : !llvm.ptr<3> -> vector<32xf32>
-//  RDNA3-COUNT-32:    llvm.load {{.*}} : !llvm.ptr<3> -> vector<16xf32>
+//   RDNA3-COUNT-1:    llvm.load {{.*}} : !llvm.ptr<1> -> vector<32xf32>
+//  RDNA3-COUNT-32:    llvm.load {{.*}} : !llvm.ptr<1> -> vector<16xf32>
 //  RDNA3-COUNT-32:    llvm.intr.fmuladd({{.*}}) : (vector<16xf32>, vector<16xf32>, vector<16xf32>) -> vector<16xf32>
 //   RDNA3-COUNT-1:    llvm.store {{.*}} : vector<16xf32>, !llvm.ptr<1>
 //           RDNA3:   llvm.br