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Revert "[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (llvm#119461)"
This reverts commit 169c32e.
1 parent 9ab16d4 commit 79ea81d

35 files changed

+267
-178
lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ static cl::opt<bool> EnablePostMISchedLoadStoreClustering(
105105
static cl::opt<bool>
106106
EnableVLOptimizer("riscv-enable-vl-optimizer",
107107
cl::desc("Enable the RISC-V VL Optimizer pass"),
108-
cl::init(true), cl::Hidden);
108+
cl::init(false), cl::Hidden);
109109

110110
static cl::opt<bool> DisableVectorMaskMutation(
111111
"riscv-disable-vector-mask-mutation",

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

+1-2
Original file line numberDiff line numberDiff line change
@@ -119,8 +119,6 @@
119119
; RV64-NEXT: RISC-V Optimize W Instructions
120120
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
121121
; CHECK-NEXT: RISC-V Merge Base Offset
122-
; CHECK-NEXT: MachineDominator Tree Construction
123-
; CHECK-NEXT: RISC-V VL Optimizer
124122
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
125123
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
126124
; CHECK-NEXT: RISC-V Landing Pad Setup
@@ -131,6 +129,7 @@
131129
; CHECK-NEXT: Live Variable Analysis
132130
; CHECK-NEXT: Eliminate PHI nodes for register allocation
133131
; CHECK-NEXT: Two-Address instruction pass
132+
; CHECK-NEXT: MachineDominator Tree Construction
134133
; CHECK-NEXT: Slot index numbering
135134
; CHECK-NEXT: Live Interval Analysis
136135
; CHECK-NEXT: Register Coalescer

‎llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll

+4-2
Original file line numberDiff line numberDiff line change
@@ -2654,8 +2654,9 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26542654
; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9:
26552655
; CHECK: # %bb.0:
26562656
; CHECK-NEXT: li a1, 511
2657-
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2657+
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
26582658
; CHECK-NEXT: vxor.vx v8, v8, a1
2659+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
26592660
; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
26602661
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
26612662
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -2669,8 +2670,9 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26692670
; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9:
26702671
; CHECK-ZVBB: # %bb.0:
26712672
; CHECK-ZVBB-NEXT: li a1, 511
2672-
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2673+
; CHECK-ZVBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
26732674
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1
2675+
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
26742676
; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
26752677
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
26762678
; CHECK-ZVBB-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

+2
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,9 @@ define void @abs_v6i16(ptr %x) {
3939
; CHECK: # %bb.0:
4040
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4141
; CHECK-NEXT: vle16.v v8, (a0)
42+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
4243
; CHECK-NEXT: vrsub.vi v9, v8, 0
44+
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4345
; CHECK-NEXT: vmax.vv v8, v8, v9
4446
; CHECK-NEXT: vse16.v v8, (a0)
4547
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

+16-4
Original file line numberDiff line numberDiff line change
@@ -788,9 +788,11 @@ define void @copysign_v6bf16(ptr %x, ptr %y) {
788788
; CHECK-NEXT: vle16.v v8, (a1)
789789
; CHECK-NEXT: vle16.v v9, (a0)
790790
; CHECK-NEXT: lui a1, 8
791+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
791792
; CHECK-NEXT: vand.vx v8, v8, a1
792793
; CHECK-NEXT: addi a1, a1, -1
793794
; CHECK-NEXT: vand.vx v9, v9, a1
795+
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
794796
; CHECK-NEXT: vor.vv v8, v9, v8
795797
; CHECK-NEXT: vse16.v v8, (a0)
796798
; CHECK-NEXT: ret
@@ -846,9 +848,11 @@ define void @copysign_v6f16(ptr %x, ptr %y) {
846848
; ZVFHMIN-NEXT: vle16.v v8, (a1)
847849
; ZVFHMIN-NEXT: vle16.v v9, (a0)
848850
; ZVFHMIN-NEXT: lui a1, 8
851+
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
849852
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
850853
; ZVFHMIN-NEXT: addi a1, a1, -1
851854
; ZVFHMIN-NEXT: vand.vx v9, v9, a1
855+
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
852856
; ZVFHMIN-NEXT: vor.vv v8, v9, v8
853857
; ZVFHMIN-NEXT: vse16.v v8, (a0)
854858
; ZVFHMIN-NEXT: ret
@@ -920,10 +924,12 @@ define void @copysign_vf_v6bf16(ptr %x, bfloat %y) {
920924
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
921925
; CHECK-NEXT: vle16.v v8, (a0)
922926
; CHECK-NEXT: lui a2, 8
927+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
923928
; CHECK-NEXT: vmv.v.x v9, a1
924929
; CHECK-NEXT: addi a1, a2, -1
925930
; CHECK-NEXT: vand.vx v8, v8, a1
926931
; CHECK-NEXT: vand.vx v9, v9, a2
932+
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
927933
; CHECK-NEXT: vor.vv v8, v8, v9
928934
; CHECK-NEXT: vse16.v v8, (a0)
929935
; CHECK-NEXT: ret
@@ -980,10 +986,12 @@ define void @copysign_vf_v6f16(ptr %x, half %y) {
980986
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
981987
; ZVFHMIN-NEXT: vle16.v v8, (a0)
982988
; ZVFHMIN-NEXT: lui a2, 8
989+
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
983990
; ZVFHMIN-NEXT: vmv.v.x v9, a1
984991
; ZVFHMIN-NEXT: addi a1, a2, -1
985992
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
986993
; ZVFHMIN-NEXT: vand.vx v9, v9, a2
994+
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
987995
; ZVFHMIN-NEXT: vor.vv v8, v8, v9
988996
; ZVFHMIN-NEXT: vse16.v v8, (a0)
989997
; ZVFHMIN-NEXT: ret
@@ -1057,9 +1065,11 @@ define void @copysign_neg_v6bf16(ptr %x, ptr %y) {
10571065
; CHECK-NEXT: vle16.v v9, (a0)
10581066
; CHECK-NEXT: lui a1, 8
10591067
; CHECK-NEXT: addi a2, a1, -1
1068+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
10601069
; CHECK-NEXT: vxor.vx v8, v8, a1
10611070
; CHECK-NEXT: vand.vx v9, v9, a2
10621071
; CHECK-NEXT: vand.vx v8, v8, a1
1072+
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
10631073
; CHECK-NEXT: vor.vv v8, v9, v8
10641074
; CHECK-NEXT: vse16.v v8, (a0)
10651075
; CHECK-NEXT: ret
@@ -1119,9 +1129,11 @@ define void @copysign_neg_v6f16(ptr %x, ptr %y) {
11191129
; ZVFHMIN-NEXT: vle16.v v9, (a0)
11201130
; ZVFHMIN-NEXT: lui a1, 8
11211131
; ZVFHMIN-NEXT: addi a2, a1, -1
1132+
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11221133
; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
11231134
; ZVFHMIN-NEXT: vand.vx v9, v9, a2
11241135
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
1136+
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
11251137
; ZVFHMIN-NEXT: vor.vv v8, v9, v8
11261138
; ZVFHMIN-NEXT: vse16.v v8, (a0)
11271139
; ZVFHMIN-NEXT: ret
@@ -1199,12 +1211,12 @@ define void @copysign_neg_trunc_v3bf16_v3f32(ptr %x, ptr %y) {
11991211
; CHECK-NEXT: vle32.v v9, (a1)
12001212
; CHECK-NEXT: lui a1, 8
12011213
; CHECK-NEXT: addi a2, a1, -1
1202-
; CHECK-NEXT: vand.vx v8, v8, a2
12031214
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
1215+
; CHECK-NEXT: vand.vx v8, v8, a2
12041216
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v9
1205-
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12061217
; CHECK-NEXT: vxor.vx v9, v10, a1
12071218
; CHECK-NEXT: vand.vx v9, v9, a1
1219+
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12081220
; CHECK-NEXT: vor.vv v8, v8, v9
12091221
; CHECK-NEXT: vse16.v v8, (a0)
12101222
; CHECK-NEXT: ret
@@ -1271,12 +1283,12 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
12711283
; ZVFHMIN-NEXT: vle32.v v9, (a1)
12721284
; ZVFHMIN-NEXT: lui a1, 8
12731285
; ZVFHMIN-NEXT: addi a2, a1, -1
1274-
; ZVFHMIN-NEXT: vand.vx v8, v8, a2
12751286
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
1287+
; ZVFHMIN-NEXT: vand.vx v8, v8, a2
12761288
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
1277-
; ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12781289
; ZVFHMIN-NEXT: vxor.vx v9, v10, a1
12791290
; ZVFHMIN-NEXT: vand.vx v9, v9, a1
1291+
; ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12801292
; ZVFHMIN-NEXT: vor.vv v8, v8, v9
12811293
; ZVFHMIN-NEXT: vse16.v v8, (a0)
12821294
; ZVFHMIN-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

+1-2
Original file line numberDiff line numberDiff line change
@@ -910,9 +910,8 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() {
910910
define <16 x i8> @buildvec_not_vid_v16i8() {
911911
; CHECK-LABEL: buildvec_not_vid_v16i8:
912912
; CHECK: # %bb.0:
913-
; CHECK-NEXT: vsetivli zero, 7, e8, m1, ta, ma
914-
; CHECK-NEXT: vmv.v.i v9, 3
915913
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
914+
; CHECK-NEXT: vmv.v.i v9, 3
916915
; CHECK-NEXT: vmv.v.i v8, 0
917916
; CHECK-NEXT: vsetivli zero, 7, e8, m1, tu, ma
918917
; CHECK-NEXT: vslideup.vi v8, v9, 6

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

+2-4
Original file line numberDiff line numberDiff line change
@@ -348,9 +348,8 @@ define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) {
348348
define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) {
349349
; CHECK-LABEL: splat_ve4_ins_i1ve3:
350350
; CHECK: # %bb.0:
351-
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, ma
352-
; CHECK-NEXT: vmv.v.i v9, 3
353351
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
352+
; CHECK-NEXT: vmv.v.i v9, 3
354353
; CHECK-NEXT: vmv.v.i v10, 4
355354
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
356355
; CHECK-NEXT: vslideup.vi v10, v9, 1
@@ -433,9 +432,8 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
433432
define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
434433
; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
435434
; CHECK: # %bb.0:
436-
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, ta, ma
437-
; CHECK-NEXT: vmv.v.i v10, 4
438435
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
436+
; CHECK-NEXT: vmv.v.i v10, 4
439437
; CHECK-NEXT: vmv.v.i v11, 0
440438
; CHECK-NEXT: li a0, 70
441439
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

+1-3
Original file line numberDiff line numberDiff line change
@@ -1100,17 +1100,15 @@ define void @mulhu_v8i16(ptr %x) {
11001100
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11011101
; CHECK-NEXT: vle16.v v8, (a0)
11021102
; CHECK-NEXT: vmv.v.i v9, 0
1103-
; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, ma
11041103
; CHECK-NEXT: vmv.v.i v10, 1
11051104
; CHECK-NEXT: li a1, 33
11061105
; CHECK-NEXT: vmv.s.x v0, a1
11071106
; CHECK-NEXT: lui a1, %hi(.LCPI66_0)
11081107
; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0)
1109-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11101108
; CHECK-NEXT: vmv.v.i v11, 3
11111109
; CHECK-NEXT: vle16.v v12, (a1)
11121110
; CHECK-NEXT: vmerge.vim v11, v11, 2, v0
1113-
; CHECK-NEXT: vmv1r.v v13, v9
1111+
; CHECK-NEXT: vmv.v.i v13, 0
11141112
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
11151113
; CHECK-NEXT: vslideup.vi v9, v10, 6
11161114
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll

+1-2
Original file line numberDiff line numberDiff line change
@@ -97,9 +97,8 @@ define <4 x i32> @v4i32_v8i32(<8 x i32>) {
9797
define <4 x i32> @v4i32_v16i32(<16 x i32>) {
9898
; RV32-LABEL: v4i32_v16i32:
9999
; RV32: # %bb.0:
100-
; RV32-NEXT: vsetivli zero, 2, e16, m1, ta, ma
101-
; RV32-NEXT: vmv.v.i v12, 1
102100
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
101+
; RV32-NEXT: vmv.v.i v12, 1
103102
; RV32-NEXT: vmv.v.i v14, 6
104103
; RV32-NEXT: li a0, 32
105104
; RV32-NEXT: vmv.v.i v0, 10

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