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LoongArchAsmParser.cpp
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// LoongArchAsmParser.cpp - Parse LoongArch assembly to MCInst instructions -=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/LoongArchBaseInfo.h"
#include "MCTargetDesc/LoongArchInstPrinter.h"
#include "MCTargetDesc/LoongArchMCExpr.h"
#include "MCTargetDesc/LoongArchMCTargetDesc.h"
#include "MCTargetDesc/LoongArchMatInt.h"
#include "MCTargetDesc/LoongArchTargetStreamer.h"
#include "TargetInfo/LoongArchTargetInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCValue.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Casting.h"
using namespace llvm;
#define DEBUG_TYPE "loongarch-asm-parser"
namespace {
class LoongArchAsmParser : public MCTargetAsmParser {
SmallVector<FeatureBitset, 4> FeatureBitStack;
SMLoc getLoc() const { return getParser().getTok().getLoc(); }
bool is64Bit() const { return getSTI().hasFeature(LoongArch::Feature64Bit); }
LoongArchTargetStreamer &getTargetStreamer() {
assert(getParser().getStreamer().getTargetStreamer() &&
"do not have a target streamer");
MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
return static_cast<LoongArchTargetStreamer &>(TS);
}
struct Inst {
unsigned Opc;
LoongArchMCExpr::VariantKind VK;
Inst(unsigned Opc,
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None)
: Opc(Opc), VK(VK) {}
};
using InstSeq = SmallVector<Inst>;
/// Parse a register as used in CFI directives.
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
unsigned checkTargetMatchPredicate(MCInst &Inst) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override;
ParseStatus parseDirective(AsmToken DirectiveID) override;
bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo,
int64_t Lower, int64_t Upper,
const Twine &Msg);
/// Helper for processing MC instructions that have been successfully matched
/// by matchAndEmitInstruction.
bool processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands,
MCStreamer &Out);
// Auto-generated instruction matching functions.
#define GET_ASSEMBLER_HEADER
#include "LoongArchGenAsmMatcher.inc"
ParseStatus parseRegister(OperandVector &Operands);
ParseStatus parseImmediate(OperandVector &Operands);
ParseStatus parseOperandWithModifier(OperandVector &Operands);
ParseStatus parseSImm26Operand(OperandVector &Operands);
ParseStatus parseAtomicMemOp(OperandVector &Operands);
bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
bool parseDirectiveOption();
void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
if (!(getSTI().hasFeature(Feature))) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
}
}
void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
if (getSTI().hasFeature(Feature)) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
}
}
void pushFeatureBits() {
FeatureBitStack.push_back(getSTI().getFeatureBits());
}
bool popFeatureBits() {
if (FeatureBitStack.empty())
return true;
FeatureBitset FeatureBits = FeatureBitStack.pop_back_val();
copySTI().setFeatureBits(FeatureBits);
setAvailableFeatures(ComputeAvailableFeatures(FeatureBits));
return false;
}
// Helper to emit the sequence of instructions generated by the
// "emitLoadAddress*" functions.
void emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
const MCExpr *Symbol, SmallVectorImpl<Inst> &Insts,
SMLoc IDLoc, MCStreamer &Out, bool RelaxHint = false);
// Helper to emit pseudo instruction "la.abs $rd, sym".
void emitLoadAddressAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.pcrel $rd, sym".
void emitLoadAddressPcrel(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.pcrel $rd, $rj, sym".
void emitLoadAddressPcrelLarge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.got $rd, sym".
void emitLoadAddressGot(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.got $rd, $rj, sym".
void emitLoadAddressGotLarge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.tls.le $rd, sym".
void emitLoadAddressTLSLE(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.tls.ie $rd, sym".
void emitLoadAddressTLSIE(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.tls.ie $rd, $rj, sym".
void emitLoadAddressTLSIELarge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.tls.ld $rd, sym".
void emitLoadAddressTLSLD(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.tls.ld $rd, $rj, sym".
void emitLoadAddressTLSLDLarge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.tls.gd $rd, sym".
void emitLoadAddressTLSGD(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.tls.gd $rd, $rj, sym".
void emitLoadAddressTLSGDLarge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.tls.desc $rd, sym".
void emitLoadAddressTLSDesc(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "la.tls.desc $rd, $rj, sym".
void emitLoadAddressTLSDescLarge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "li.w/d $rd, $imm".
void emitLoadImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
// Helper to emit pseudo instruction "call36 sym" or "tail36 $rj, sym".
void emitFuncCall36(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
bool IsTailCall);
public:
enum LoongArchMatchResultTy {
Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
Match_RequiresMsbNotLessThanLsb,
Match_RequiresOpnd2NotR0R1,
Match_RequiresAMORdDifferRkRj,
Match_RequiresLAORdDifferRj,
Match_RequiresLAORdR4,
#define GET_OPERAND_DIAGNOSTIC_TYPES
#include "LoongArchGenAsmMatcher.inc"
#undef GET_OPERAND_DIAGNOSTIC_TYPES
};
static bool classifySymbolRef(const MCExpr *Expr,
LoongArchMCExpr::VariantKind &Kind);
LoongArchAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI, MII) {
Parser.addAliasForDirective(".half", ".2byte");
Parser.addAliasForDirective(".hword", ".2byte");
Parser.addAliasForDirective(".word", ".4byte");
Parser.addAliasForDirective(".dword", ".8byte");
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
}
};
// Instances of this class represent a parsed LoongArch machine instruction.
class LoongArchOperand : public MCParsedAsmOperand {
enum class KindTy {
Token,
Register,
Immediate,
} Kind;
struct RegOp {
MCRegister RegNum;
};
struct ImmOp {
const MCExpr *Val;
};
SMLoc StartLoc, EndLoc;
union {
StringRef Tok;
struct RegOp Reg;
struct ImmOp Imm;
};
public:
LoongArchOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
bool isToken() const override { return Kind == KindTy::Token; }
bool isReg() const override { return Kind == KindTy::Register; }
bool isImm() const override { return Kind == KindTy::Immediate; }
bool isMem() const override { return false; }
void setReg(MCRegister PhysReg) { Reg.RegNum = PhysReg; }
bool isGPR() const {
return Kind == KindTy::Register &&
LoongArchMCRegisterClasses[LoongArch::GPRRegClassID].contains(
Reg.RegNum);
}
static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
LoongArchMCExpr::VariantKind &VK) {
if (auto *LE = dyn_cast<LoongArchMCExpr>(Expr)) {
VK = LE->getKind();
return false;
}
if (auto CE = dyn_cast<MCConstantExpr>(Expr)) {
Imm = CE->getValue();
return true;
}
return false;
}
template <unsigned N, int P = 0> bool isUImm() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
return IsConstantImm && isUInt<N>(Imm - P) &&
VK == LoongArchMCExpr::VK_LoongArch_None;
}
template <unsigned N, unsigned S = 0> bool isSImm() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
return IsConstantImm && isShiftedInt<N, S>(Imm) &&
VK == LoongArchMCExpr::VK_LoongArch_None;
}
bool isBareSymbol() const {
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
// Must be of 'immediate' type but not a constant.
if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
return false;
return LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
VK == LoongArchMCExpr::VK_LoongArch_None;
}
bool isTPRelAddSymbol() const {
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
// Must be of 'immediate' type but not a constant.
if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
return false;
return LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
VK == LoongArchMCExpr::VK_LoongArch_TLS_LE_ADD_R;
}
bool isUImm1() const { return isUImm<1>(); }
bool isUImm2() const { return isUImm<2>(); }
bool isUImm2plus1() const { return isUImm<2, 1>(); }
bool isUImm3() const { return isUImm<3>(); }
bool isUImm4() const { return isUImm<4>(); }
bool isSImm5() const { return isSImm<5>(); }
bool isUImm5() const { return isUImm<5>(); }
bool isUImm6() const { return isUImm<6>(); }
bool isUImm7() const { return isUImm<7>(); }
bool isSImm8() const { return isSImm<8>(); }
bool isSImm8lsl1() const { return isSImm<8, 1>(); }
bool isSImm8lsl2() const { return isSImm<8, 2>(); }
bool isSImm8lsl3() const { return isSImm<8, 3>(); }
bool isUImm8() const { return isUImm<8>(); }
bool isSImm9lsl3() const { return isSImm<9, 3>(); }
bool isSImm10() const { return isSImm<10>(); }
bool isSImm10lsl2() const { return isSImm<10, 2>(); }
bool isSImm11lsl1() const { return isSImm<11, 1>(); }
bool isSImm12() const { return isSImm<12>(); }
bool isSImm12addlike() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_PCALA_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_IE_PC_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_LE_LO12_R ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC_PC_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC_LD;
return IsConstantImm
? isInt<12>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isSImm12lu52id() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_ABS64_HI12 ||
VK == LoongArchMCExpr::VK_LoongArch_PCALA64_HI12 ||
VK == LoongArchMCExpr::VK_LoongArch_GOT64_HI12 ||
VK == LoongArchMCExpr::VK_LoongArch_GOT64_PC_HI12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_LE64_HI12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_IE64_HI12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_IE64_PC_HI12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC64_HI12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC64_PC_HI12;
return IsConstantImm
? isInt<12>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isUImm12() const { return isUImm<12>(); }
bool isUImm12ori() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_ABS_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_PCALA_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_GOT_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_LE_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_IE_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_IE_PC_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC_LO12;
return IsConstantImm
? isUInt<12>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isSImm13() const { return isSImm<13>(); }
bool isUImm14() const { return isUImm<14>(); }
bool isUImm15() const { return isUImm<15>(); }
bool isSImm14lsl2() const { return isSImm<14, 2>(); }
bool isSImm16() const { return isSImm<16>(); }
bool isSImm16lsl2() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_B16 ||
VK == LoongArchMCExpr::VK_LoongArch_PCALA_LO12 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC_CALL;
return IsConstantImm
? isShiftedInt<16, 2>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isSImm20() const { return isSImm<20>(); }
bool isSImm20pcalau12i() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_PCALA_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_GOT_PC_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_IE_PC_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_LD_PC_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_GD_PC_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC_PC_HI20;
return IsConstantImm
? isInt<20>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isSImm20lu12iw() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_ABS_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_GOT_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_GD_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_LD_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_IE_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_LE_HI20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_LE_HI20_R ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC_HI20;
return IsConstantImm
? isInt<20>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isSImm20lu32id() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_ABS64_LO20 ||
VK == LoongArchMCExpr::VK_LoongArch_PCALA64_LO20 ||
VK == LoongArchMCExpr::VK_LoongArch_GOT64_LO20 ||
VK == LoongArchMCExpr::VK_LoongArch_GOT64_PC_LO20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_IE64_LO20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_IE64_PC_LO20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_LE64_LO20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC64_PC_LO20 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC64_LO20;
return IsConstantImm
? isInt<20>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isSImm20pcaddu18i() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_CALL36;
return IsConstantImm
? isInt<20>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isSImm20pcaddi() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_PCREL20_S2 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_LD_PCREL20_S2 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_GD_PCREL20_S2 ||
VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC_PCREL20_S2;
return IsConstantImm
? isInt<20>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isSImm21lsl2() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_B21;
return IsConstantImm
? isShiftedInt<21, 2>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isSImm26Operand() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_None ||
VK == LoongArchMCExpr::VK_LoongArch_CALL ||
VK == LoongArchMCExpr::VK_LoongArch_CALL_PLT ||
VK == LoongArchMCExpr::VK_LoongArch_B26;
return IsConstantImm
? isShiftedInt<26, 2>(Imm) && IsValidKind
: LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
IsValidKind;
}
bool isImm32() const { return isSImm<32>() || isUImm<32>(); }
bool isImm64() const {
if (!isImm())
return false;
int64_t Imm;
LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
return IsConstantImm && VK == LoongArchMCExpr::VK_LoongArch_None;
}
/// Gets location of the first token of this operand.
SMLoc getStartLoc() const override { return StartLoc; }
/// Gets location of the last token of this operand.
SMLoc getEndLoc() const override { return EndLoc; }
MCRegister getReg() const override {
assert(Kind == KindTy::Register && "Invalid type access!");
return Reg.RegNum;
}
const MCExpr *getImm() const {
assert(Kind == KindTy::Immediate && "Invalid type access!");
return Imm.Val;
}
StringRef getToken() const {
assert(Kind == KindTy::Token && "Invalid type access!");
return Tok;
}
void print(raw_ostream &OS) const override {
auto RegName = [](MCRegister Reg) {
if (Reg)
return LoongArchInstPrinter::getRegisterName(Reg);
else
return "noreg";
};
switch (Kind) {
case KindTy::Immediate:
OS << *getImm();
break;
case KindTy::Register:
OS << "<register " << RegName(getReg()) << ">";
break;
case KindTy::Token:
OS << "'" << getToken() << "'";
break;
}
}
static std::unique_ptr<LoongArchOperand> createToken(StringRef Str, SMLoc S) {
auto Op = std::make_unique<LoongArchOperand>(KindTy::Token);
Op->Tok = Str;
Op->StartLoc = S;
Op->EndLoc = S;
return Op;
}
static std::unique_ptr<LoongArchOperand> createReg(MCRegister Reg, SMLoc S,
SMLoc E) {
auto Op = std::make_unique<LoongArchOperand>(KindTy::Register);
Op->Reg.RegNum = Reg;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
}
static std::unique_ptr<LoongArchOperand> createImm(const MCExpr *Val, SMLoc S,
SMLoc E) {
auto Op = std::make_unique<LoongArchOperand>(KindTy::Immediate);
Op->Imm.Val = Val;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
}
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
if (auto CE = dyn_cast<MCConstantExpr>(Expr))
Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
Inst.addOperand(MCOperand::createExpr(Expr));
}
// Used by the TableGen Code.
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(getReg()));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
addExpr(Inst, getImm());
}
};
} // end namespace
#define GET_REGISTER_MATCHER
#define GET_SUBTARGET_FEATURE_NAME
#define GET_MATCHER_IMPLEMENTATION
#define GET_MNEMONIC_SPELL_CHECKER
#include "LoongArchGenAsmMatcher.inc"
static MCRegister convertFPR32ToFPR64(MCRegister Reg) {
assert(Reg >= LoongArch::F0 && Reg <= LoongArch::F31 && "Invalid register");
return Reg - LoongArch::F0 + LoongArch::F0_64;
}
// Attempts to match Name as a register (either using the default name or
// alternative ABI names), setting RegNo to the matching register. Upon
// failure, returns true and sets RegNo to 0.
static bool matchRegisterNameHelper(MCRegister &RegNo, StringRef Name) {
RegNo = MatchRegisterName(Name);
// The 32-bit and 64-bit FPRs have the same asm name. Check that the initial
// match always matches the 32-bit variant, and not the 64-bit one.
assert(!(RegNo >= LoongArch::F0_64 && RegNo <= LoongArch::F31_64));
// The default FPR register class is based on the tablegen enum ordering.
static_assert(LoongArch::F0 < LoongArch::F0_64,
"FPR matching must be updated");
if (RegNo == LoongArch::NoRegister)
RegNo = MatchRegisterAltName(Name);
return RegNo == LoongArch::NoRegister;
}
bool LoongArchAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) {
if (!tryParseRegister(Reg, StartLoc, EndLoc).isSuccess())
return Error(getLoc(), "invalid register name");
if (!LoongArchMCRegisterClasses[LoongArch::GPRRegClassID].contains(Reg) &&
!LoongArchMCRegisterClasses[LoongArch::FPR32RegClassID].contains(Reg))
return Error(getLoc(), "invalid register name");
return false;
}
ParseStatus LoongArchAsmParser::tryParseRegister(MCRegister &Reg,
SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken &Tok = getParser().getTok();
StartLoc = Tok.getLoc();
EndLoc = Tok.getEndLoc();
parseOptionalToken(AsmToken::Dollar);
if (getLexer().getKind() != AsmToken::Identifier)
return ParseStatus::NoMatch;
StringRef Name = Tok.getIdentifier();
if (matchRegisterNameHelper(Reg, Name))
return ParseStatus::NoMatch;
getParser().Lex(); // Eat identifier token.
return ParseStatus::Success;
}
bool LoongArchAsmParser::classifySymbolRef(const MCExpr *Expr,
LoongArchMCExpr::VariantKind &Kind) {
Kind = LoongArchMCExpr::VK_LoongArch_None;
if (const LoongArchMCExpr *RE = dyn_cast<LoongArchMCExpr>(Expr)) {
Kind = RE->getKind();
Expr = RE->getSubExpr();
}
MCValue Res;
if (Expr->evaluateAsRelocatable(Res, nullptr, nullptr))
return Res.getRefKind() == LoongArchMCExpr::VK_LoongArch_None;
return false;
}
ParseStatus LoongArchAsmParser::parseRegister(OperandVector &Operands) {
if (!parseOptionalToken(AsmToken::Dollar))
return ParseStatus::NoMatch;
if (getLexer().getKind() != AsmToken::Identifier)
return ParseStatus::NoMatch;
StringRef Name = getLexer().getTok().getIdentifier();
MCRegister RegNo;
matchRegisterNameHelper(RegNo, Name);
if (RegNo == LoongArch::NoRegister)
return ParseStatus::NoMatch;
SMLoc S = getLoc();
SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
getLexer().Lex();
Operands.push_back(LoongArchOperand::createReg(RegNo, S, E));
return ParseStatus::Success;
}
ParseStatus LoongArchAsmParser::parseImmediate(OperandVector &Operands) {
SMLoc S = getLoc();
SMLoc E;
const MCExpr *Res;
switch (getLexer().getKind()) {
default:
return ParseStatus::NoMatch;
case AsmToken::LParen:
case AsmToken::Dot:
case AsmToken::Minus:
case AsmToken::Plus:
case AsmToken::Exclaim:
case AsmToken::Tilde:
case AsmToken::Integer:
case AsmToken::String:
case AsmToken::Identifier:
if (getParser().parseExpression(Res, E))
return ParseStatus::Failure;
break;
case AsmToken::Percent:
return parseOperandWithModifier(Operands);
}
Operands.push_back(LoongArchOperand::createImm(Res, S, E));
return ParseStatus::Success;
}
ParseStatus
LoongArchAsmParser::parseOperandWithModifier(OperandVector &Operands) {
SMLoc S = getLoc();
SMLoc E;
if (getLexer().getKind() != AsmToken::Percent)
return Error(getLoc(), "expected '%' for operand modifier");
getParser().Lex(); // Eat '%'
if (getLexer().getKind() != AsmToken::Identifier)
return Error(getLoc(), "expected valid identifier for operand modifier");
StringRef Identifier = getParser().getTok().getIdentifier();
LoongArchMCExpr::VariantKind VK =
LoongArchMCExpr::getVariantKindForName(Identifier);
if (VK == LoongArchMCExpr::VK_LoongArch_Invalid)
return Error(getLoc(), "unrecognized operand modifier");
getParser().Lex(); // Eat the identifier
if (getLexer().getKind() != AsmToken::LParen)
return Error(getLoc(), "expected '('");
getParser().Lex(); // Eat '('
const MCExpr *SubExpr;
if (getParser().parseParenExpression(SubExpr, E))
return ParseStatus::Failure;
const MCExpr *ModExpr = LoongArchMCExpr::create(SubExpr, VK, getContext());
Operands.push_back(LoongArchOperand::createImm(ModExpr, S, E));
return ParseStatus::Success;
}
ParseStatus LoongArchAsmParser::parseSImm26Operand(OperandVector &Operands) {
SMLoc S = getLoc();
const MCExpr *Res;
if (getLexer().getKind() == AsmToken::Percent)
return parseOperandWithModifier(Operands);
if (getLexer().getKind() != AsmToken::Identifier)
return ParseStatus::NoMatch;
StringRef Identifier;
if (getParser().parseIdentifier(Identifier))
return ParseStatus::Failure;
SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
Res = LoongArchMCExpr::create(Res, LoongArchMCExpr::VK_LoongArch_CALL,
getContext());
Operands.push_back(LoongArchOperand::createImm(Res, S, E));
return ParseStatus::Success;
}
ParseStatus LoongArchAsmParser::parseAtomicMemOp(OperandVector &Operands) {
// Parse "$r*".
if (!parseRegister(Operands).isSuccess())
return ParseStatus::NoMatch;
// If there is a next operand and it is 0, ignore it. Otherwise print a
// diagnostic message.
if (parseOptionalToken(AsmToken::Comma)) {
int64_t ImmVal;
SMLoc ImmStart = getLoc();
if (getParser().parseIntToken(ImmVal, "expected optional integer offset"))
return ParseStatus::Failure;
if (ImmVal)
return Error(ImmStart, "optional integer offset must be 0");
}
return ParseStatus::Success;
}
/// Looks at a token type and creates the relevant operand from this
/// information, adding to Operands. Return true upon an error.
bool LoongArchAsmParser::parseOperand(OperandVector &Operands,
StringRef Mnemonic) {
// Check if the current operand has a custom associated parser, if so, try to
// custom parse the operand, or fallback to the general approach.
ParseStatus Result =
MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/true);
if (Result.isSuccess())
return false;
if (Result.isFailure())
return true;
if (parseRegister(Operands).isSuccess() ||
parseImmediate(Operands).isSuccess())
return false;
// Finally we have exhausted all options and must declare defeat.
return Error(getLoc(), "unknown operand");
}
bool LoongArchAsmParser::parseInstruction(ParseInstructionInfo &Info,
StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
// First operand in MCInst is instruction mnemonic.
Operands.push_back(LoongArchOperand::createToken(Name, NameLoc));
// If there are no more operands, then finish.
if (parseOptionalToken(AsmToken::EndOfStatement))
return false;
// Parse first operand.
if (parseOperand(Operands, Name))
return true;
// Parse until end of statement, consuming commas between operands.
while (parseOptionalToken(AsmToken::Comma))
if (parseOperand(Operands, Name))
return true;
// Parse end of statement and return successfully.
if (parseOptionalToken(AsmToken::EndOfStatement))
return false;
SMLoc Loc = getLexer().getLoc();
getParser().eatToEndOfStatement();
return Error(Loc, "unexpected token");
}
void LoongArchAsmParser::emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
const MCExpr *Symbol,
SmallVectorImpl<Inst> &Insts,
SMLoc IDLoc, MCStreamer &Out,
bool RelaxHint) {
MCContext &Ctx = getContext();
for (LoongArchAsmParser::Inst &Inst : Insts) {
unsigned Opc = Inst.Opc;
LoongArchMCExpr::VariantKind VK = Inst.VK;
const LoongArchMCExpr *LE =
LoongArchMCExpr::create(Symbol, VK, Ctx, RelaxHint);
switch (Opc) {
default:
llvm_unreachable("unexpected opcode");
case LoongArch::PCALAU12I:
case LoongArch::LU12I_W:
Out.emitInstruction(MCInstBuilder(Opc).addReg(DestReg).addExpr(LE),
getSTI());
break;
case LoongArch::ORI:
case LoongArch::ADDI_W:
case LoongArch::LD_W:
case LoongArch::LD_D: {
if (VK == LoongArchMCExpr::VK_LoongArch_None) {
Out.emitInstruction(
MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addImm(0),
getSTI());
continue;
} else if (VK == LoongArchMCExpr::VK_LoongArch_TLS_DESC_LD) {
Out.emitInstruction(MCInstBuilder(Opc)
.addReg(LoongArch::R1)
.addReg(DestReg)
.addExpr(LE),
getSTI());
continue;
}
Out.emitInstruction(
MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addExpr(LE),
getSTI());
break;
}
case LoongArch::LU32I_D:
Out.emitInstruction(MCInstBuilder(Opc)
.addReg(DestReg == TmpReg ? DestReg : TmpReg)
.addReg(DestReg == TmpReg ? DestReg : TmpReg)
.addExpr(LE),
getSTI());
break;
case LoongArch::LU52I_D:
Out.emitInstruction(
MCInstBuilder(Opc).addReg(TmpReg).addReg(TmpReg).addExpr(LE),
getSTI());
break;
case LoongArch::ADDI_D:
Out.emitInstruction(
MCInstBuilder(Opc)
.addReg(TmpReg)
.addReg(DestReg == TmpReg ? TmpReg : LoongArch::R0)
.addExpr(LE),
getSTI());
break;
case LoongArch::ADD_D:
case LoongArch::LDX_D:
Out.emitInstruction(
MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addReg(TmpReg),
getSTI());
break;
case LoongArch::JIRL:
Out.emitInstruction(MCInstBuilder(Opc)
.addReg(LoongArch::R1)
.addReg(LoongArch::R1)
.addExpr(LE),
getSTI());
break;
}
}
}
void LoongArchAsmParser::emitLoadAddressAbs(MCInst &Inst, SMLoc IDLoc,
MCStreamer &Out) {
// la.abs $rd, sym
// expands to:
// lu12i.w $rd, %abs_hi20(sym)
// ori $rd, $rd, %abs_lo12(sym)
//
// for 64bit appends:
// lu32i.d $rd, %abs64_lo20(sym)
// lu52i.d $rd, $rd, %abs64_hi12(sym)
MCRegister DestReg = Inst.getOperand(0).getReg();
const MCExpr *Symbol = Inst.getOpcode() == LoongArch::PseudoLA_ABS
? Inst.getOperand(1).getExpr()
: Inst.getOperand(2).getExpr();
InstSeq Insts;
Insts.push_back(LoongArchAsmParser::Inst(
LoongArch::LU12I_W, LoongArchMCExpr::VK_LoongArch_ABS_HI20));
Insts.push_back(LoongArchAsmParser::Inst(
LoongArch::ORI, LoongArchMCExpr::VK_LoongArch_ABS_LO12));
if (is64Bit()) {
Insts.push_back(LoongArchAsmParser::Inst(
LoongArch::LU32I_D, LoongArchMCExpr::VK_LoongArch_ABS64_LO20));
Insts.push_back(LoongArchAsmParser::Inst(
LoongArch::LU52I_D, LoongArchMCExpr::VK_LoongArch_ABS64_HI12));
}
emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out);
}
void LoongArchAsmParser::emitLoadAddressPcrel(MCInst &Inst, SMLoc IDLoc,
MCStreamer &Out) {
// la.pcrel $rd, sym
// expands to:
// pcalau12i $rd, %pc_hi20(sym)