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michaelmaitlandmichaelmaitland
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[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461)
Now that we have testing of all instructions in the isSupportedInstr switch, and better coverage of getOperandInfo, I think it is a good time to enable this by default.
1 parent b0fbddd commit 169c32e

35 files changed

+178
-267
lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ static cl::opt<bool> EnablePostMISchedLoadStoreClustering(
105105
static cl::opt<bool>
106106
EnableVLOptimizer("riscv-enable-vl-optimizer",
107107
cl::desc("Enable the RISC-V VL Optimizer pass"),
108-
cl::init(false), cl::Hidden);
108+
cl::init(true), cl::Hidden);
109109

110110
static cl::opt<bool> DisableVectorMaskMutation(
111111
"riscv-disable-vector-mask-mutation",

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

+2-1
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,8 @@
119119
; RV64-NEXT: RISC-V Optimize W Instructions
120120
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
121121
; CHECK-NEXT: RISC-V Merge Base Offset
122+
; CHECK-NEXT: MachineDominator Tree Construction
123+
; CHECK-NEXT: RISC-V VL Optimizer
122124
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
123125
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
124126
; CHECK-NEXT: RISC-V Landing Pad Setup
@@ -129,7 +131,6 @@
129131
; CHECK-NEXT: Live Variable Analysis
130132
; CHECK-NEXT: Eliminate PHI nodes for register allocation
131133
; CHECK-NEXT: Two-Address instruction pass
132-
; CHECK-NEXT: MachineDominator Tree Construction
133134
; CHECK-NEXT: Slot index numbering
134135
; CHECK-NEXT: Live Interval Analysis
135136
; CHECK-NEXT: Register Coalescer

‎llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll

+2-4
Original file line numberDiff line numberDiff line change
@@ -2654,9 +2654,8 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26542654
; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9:
26552655
; CHECK: # %bb.0:
26562656
; CHECK-NEXT: li a1, 511
2657-
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2658-
; CHECK-NEXT: vxor.vx v8, v8, a1
26592657
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2658+
; CHECK-NEXT: vxor.vx v8, v8, a1
26602659
; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
26612660
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
26622661
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -2670,9 +2669,8 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26702669
; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9:
26712670
; CHECK-ZVBB: # %bb.0:
26722671
; CHECK-ZVBB-NEXT: li a1, 511
2673-
; CHECK-ZVBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2674-
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1
26752672
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2673+
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1
26762674
; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
26772675
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
26782676
; CHECK-ZVBB-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

-2
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,7 @@ define void @abs_v6i16(ptr %x) {
3939
; CHECK: # %bb.0:
4040
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4141
; CHECK-NEXT: vle16.v v8, (a0)
42-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
4342
; CHECK-NEXT: vrsub.vi v9, v8, 0
44-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4543
; CHECK-NEXT: vmax.vv v8, v8, v9
4644
; CHECK-NEXT: vse16.v v8, (a0)
4745
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

+4-16
Original file line numberDiff line numberDiff line change
@@ -788,11 +788,9 @@ define void @copysign_v6bf16(ptr %x, ptr %y) {
788788
; CHECK-NEXT: vle16.v v8, (a1)
789789
; CHECK-NEXT: vle16.v v9, (a0)
790790
; CHECK-NEXT: lui a1, 8
791-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
792791
; CHECK-NEXT: vand.vx v8, v8, a1
793792
; CHECK-NEXT: addi a1, a1, -1
794793
; CHECK-NEXT: vand.vx v9, v9, a1
795-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
796794
; CHECK-NEXT: vor.vv v8, v9, v8
797795
; CHECK-NEXT: vse16.v v8, (a0)
798796
; CHECK-NEXT: ret
@@ -848,11 +846,9 @@ define void @copysign_v6f16(ptr %x, ptr %y) {
848846
; ZVFHMIN-NEXT: vle16.v v8, (a1)
849847
; ZVFHMIN-NEXT: vle16.v v9, (a0)
850848
; ZVFHMIN-NEXT: lui a1, 8
851-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
852849
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
853850
; ZVFHMIN-NEXT: addi a1, a1, -1
854851
; ZVFHMIN-NEXT: vand.vx v9, v9, a1
855-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
856852
; ZVFHMIN-NEXT: vor.vv v8, v9, v8
857853
; ZVFHMIN-NEXT: vse16.v v8, (a0)
858854
; ZVFHMIN-NEXT: ret
@@ -924,12 +920,10 @@ define void @copysign_vf_v6bf16(ptr %x, bfloat %y) {
924920
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
925921
; CHECK-NEXT: vle16.v v8, (a0)
926922
; CHECK-NEXT: lui a2, 8
927-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
928923
; CHECK-NEXT: vmv.v.x v9, a1
929924
; CHECK-NEXT: addi a1, a2, -1
930925
; CHECK-NEXT: vand.vx v8, v8, a1
931926
; CHECK-NEXT: vand.vx v9, v9, a2
932-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
933927
; CHECK-NEXT: vor.vv v8, v8, v9
934928
; CHECK-NEXT: vse16.v v8, (a0)
935929
; CHECK-NEXT: ret
@@ -986,12 +980,10 @@ define void @copysign_vf_v6f16(ptr %x, half %y) {
986980
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
987981
; ZVFHMIN-NEXT: vle16.v v8, (a0)
988982
; ZVFHMIN-NEXT: lui a2, 8
989-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
990983
; ZVFHMIN-NEXT: vmv.v.x v9, a1
991984
; ZVFHMIN-NEXT: addi a1, a2, -1
992985
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
993986
; ZVFHMIN-NEXT: vand.vx v9, v9, a2
994-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
995987
; ZVFHMIN-NEXT: vor.vv v8, v8, v9
996988
; ZVFHMIN-NEXT: vse16.v v8, (a0)
997989
; ZVFHMIN-NEXT: ret
@@ -1065,11 +1057,9 @@ define void @copysign_neg_v6bf16(ptr %x, ptr %y) {
10651057
; CHECK-NEXT: vle16.v v9, (a0)
10661058
; CHECK-NEXT: lui a1, 8
10671059
; CHECK-NEXT: addi a2, a1, -1
1068-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
10691060
; CHECK-NEXT: vxor.vx v8, v8, a1
10701061
; CHECK-NEXT: vand.vx v9, v9, a2
10711062
; CHECK-NEXT: vand.vx v8, v8, a1
1072-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
10731063
; CHECK-NEXT: vor.vv v8, v9, v8
10741064
; CHECK-NEXT: vse16.v v8, (a0)
10751065
; CHECK-NEXT: ret
@@ -1129,11 +1119,9 @@ define void @copysign_neg_v6f16(ptr %x, ptr %y) {
11291119
; ZVFHMIN-NEXT: vle16.v v9, (a0)
11301120
; ZVFHMIN-NEXT: lui a1, 8
11311121
; ZVFHMIN-NEXT: addi a2, a1, -1
1132-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11331122
; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
11341123
; ZVFHMIN-NEXT: vand.vx v9, v9, a2
11351124
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
1136-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
11371125
; ZVFHMIN-NEXT: vor.vv v8, v9, v8
11381126
; ZVFHMIN-NEXT: vse16.v v8, (a0)
11391127
; ZVFHMIN-NEXT: ret
@@ -1211,12 +1199,12 @@ define void @copysign_neg_trunc_v3bf16_v3f32(ptr %x, ptr %y) {
12111199
; CHECK-NEXT: vle32.v v9, (a1)
12121200
; CHECK-NEXT: lui a1, 8
12131201
; CHECK-NEXT: addi a2, a1, -1
1214-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
12151202
; CHECK-NEXT: vand.vx v8, v8, a2
1203+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
12161204
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v9
1205+
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12171206
; CHECK-NEXT: vxor.vx v9, v10, a1
12181207
; CHECK-NEXT: vand.vx v9, v9, a1
1219-
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12201208
; CHECK-NEXT: vor.vv v8, v8, v9
12211209
; CHECK-NEXT: vse16.v v8, (a0)
12221210
; CHECK-NEXT: ret
@@ -1283,12 +1271,12 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
12831271
; ZVFHMIN-NEXT: vle32.v v9, (a1)
12841272
; ZVFHMIN-NEXT: lui a1, 8
12851273
; ZVFHMIN-NEXT: addi a2, a1, -1
1286-
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
12871274
; ZVFHMIN-NEXT: vand.vx v8, v8, a2
1275+
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
12881276
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
1277+
; ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12891278
; ZVFHMIN-NEXT: vxor.vx v9, v10, a1
12901279
; ZVFHMIN-NEXT: vand.vx v9, v9, a1
1291-
; ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12921280
; ZVFHMIN-NEXT: vor.vv v8, v8, v9
12931281
; ZVFHMIN-NEXT: vse16.v v8, (a0)
12941282
; ZVFHMIN-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

+2-1
Original file line numberDiff line numberDiff line change
@@ -910,8 +910,9 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() {
910910
define <16 x i8> @buildvec_not_vid_v16i8() {
911911
; CHECK-LABEL: buildvec_not_vid_v16i8:
912912
; CHECK: # %bb.0:
913-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
913+
; CHECK-NEXT: vsetivli zero, 7, e8, m1, ta, ma
914914
; CHECK-NEXT: vmv.v.i v9, 3
915+
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
915916
; CHECK-NEXT: vmv.v.i v8, 0
916917
; CHECK-NEXT: vsetivli zero, 7, e8, m1, tu, ma
917918
; CHECK-NEXT: vslideup.vi v8, v9, 6

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

+4-2
Original file line numberDiff line numberDiff line change
@@ -348,8 +348,9 @@ define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) {
348348
define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) {
349349
; CHECK-LABEL: splat_ve4_ins_i1ve3:
350350
; CHECK: # %bb.0:
351-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
351+
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, ma
352352
; CHECK-NEXT: vmv.v.i v9, 3
353+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
353354
; CHECK-NEXT: vmv.v.i v10, 4
354355
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
355356
; CHECK-NEXT: vslideup.vi v10, v9, 1
@@ -432,8 +433,9 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
432433
define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
433434
; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
434435
; CHECK: # %bb.0:
435-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
436+
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, ta, ma
436437
; CHECK-NEXT: vmv.v.i v10, 4
438+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
437439
; CHECK-NEXT: vmv.v.i v11, 0
438440
; CHECK-NEXT: li a0, 70
439441
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

+3-1
Original file line numberDiff line numberDiff line change
@@ -1100,15 +1100,17 @@ define void @mulhu_v8i16(ptr %x) {
11001100
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11011101
; CHECK-NEXT: vle16.v v8, (a0)
11021102
; CHECK-NEXT: vmv.v.i v9, 0
1103+
; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, ma
11031104
; CHECK-NEXT: vmv.v.i v10, 1
11041105
; CHECK-NEXT: li a1, 33
11051106
; CHECK-NEXT: vmv.s.x v0, a1
11061107
; CHECK-NEXT: lui a1, %hi(.LCPI66_0)
11071108
; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0)
1109+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11081110
; CHECK-NEXT: vmv.v.i v11, 3
11091111
; CHECK-NEXT: vle16.v v12, (a1)
11101112
; CHECK-NEXT: vmerge.vim v11, v11, 2, v0
1111-
; CHECK-NEXT: vmv.v.i v13, 0
1113+
; CHECK-NEXT: vmv1r.v v13, v9
11121114
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
11131115
; CHECK-NEXT: vslideup.vi v9, v10, 6
11141116
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll

+2-1
Original file line numberDiff line numberDiff line change
@@ -97,8 +97,9 @@ define <4 x i32> @v4i32_v8i32(<8 x i32>) {
9797
define <4 x i32> @v4i32_v16i32(<16 x i32>) {
9898
; RV32-LABEL: v4i32_v16i32:
9999
; RV32: # %bb.0:
100-
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
100+
; RV32-NEXT: vsetivli zero, 2, e16, m1, ta, ma
101101
; RV32-NEXT: vmv.v.i v12, 1
102+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
102103
; RV32-NEXT: vmv.v.i v14, 6
103104
; RV32-NEXT: li a0, 32
104105
; RV32-NEXT: vmv.v.i v0, 10

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