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eflash_loader.c
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typedef unsigned char undefined;
typedef unsigned char bool;
typedef unsigned char byte;
typedef unsigned int dword;
typedef long long longlong;
typedef unsigned long long qword;
typedef unsigned char uchar;
typedef unsigned int uint;
typedef unsigned long ulong;
typedef unsigned long long ulonglong;
typedef unsigned char undefined1;
typedef unsigned short undefined2;
typedef unsigned int undefined4;
typedef unsigned long long undefined8;
typedef unsigned short ushort;
typedef unsigned short word;
typedef ulong size_t;
typedef bool _Bool;
typedef undefined complex long double[32];
typedef qword complex float;
typedef undefined complex double[16];
typedef struct SPI_Flash_Cfg_Type SPI_Flash_Cfg_Type, *PSPI_Flash_Cfg_Type;
typedef uchar uint8_t;
typedef ushort uint16_t;
struct SPI_Flash_Cfg_Type {
uint8_t ioMode;
uint8_t cReadSupport;
uint8_t clkDelay;
uint8_t clkInvert;
uint8_t resetEnCmd;
uint8_t resetCmd;
uint8_t resetCreadCmd;
uint8_t resetCreadCmdSize;
uint8_t jedecIdCmd;
uint8_t jedecIdCmdDmyClk;
uint8_t qpiJedecIdCmd;
uint8_t qpiJedecIdCmdDmyClk;
uint8_t sectorSize;
uint8_t mid;
uint16_t pageSize;
uint8_t chipEraseCmd;
uint8_t sectorEraseCmd;
uint8_t blk32EraseCmd;
uint8_t blk64EraseCmd;
uint8_t writeEnableCmd;
uint8_t pageProgramCmd;
uint8_t qpageProgramCmd;
uint8_t qppAddrMode;
uint8_t fastReadCmd;
uint8_t frDmyClk;
uint8_t qpiFastReadCmd;
uint8_t qpiFrDmyClk;
uint8_t fastReadDoCmd;
uint8_t frDoDmyClk;
uint8_t fastReadDioCmd;
uint8_t frDioDmyClk;
uint8_t fastReadQoCmd;
uint8_t frQoDmyClk;
uint8_t fastReadQioCmd;
uint8_t frQioDmyClk;
uint8_t qpiFastReadQioCmd;
uint8_t qpiFrQioDmyClk;
uint8_t qpiPageProgramCmd;
uint8_t writeVregEnableCmd;
uint8_t wrEnableIndex;
uint8_t qeIndex;
uint8_t busyIndex;
uint8_t wrEnableBit;
uint8_t qeBit;
uint8_t busyBit;
uint8_t wrEnableWriteRegLen;
uint8_t wrEnableReadRegLen;
uint8_t qeWriteRegLen;
uint8_t qeReadRegLen;
uint8_t releasePowerDown;
uint8_t busyReadRegLen;
uint8_t readRegCmd[4];
uint8_t writeRegCmd[4];
uint8_t enterQpi;
uint8_t exitQpi;
uint8_t cReadMode;
uint8_t cRExit;
uint8_t burstWrapCmd;
uint8_t burstWrapCmdDmyClk;
uint8_t burstWrapDataMode;
uint8_t burstWrapData;
uint8_t deBurstWrapCmd;
uint8_t deBurstWrapCmdDmyClk;
uint8_t deBurstWrapDataMode;
uint8_t deBurstWrapData;
uint16_t timeEsector;
uint16_t timeE32k;
uint16_t timeE64k;
uint16_t timePagePgm;
uint16_t timeCe;
uint8_t pdDelay;
uint8_t qeData;
};
typedef struct UART_CFG_Type UART_CFG_Type, *PUART_CFG_Type;
typedef uint uint32_t;
typedef enum UART_DataBits_Type {
UART_DATABITS_5=0,
UART_DATABITS_6=1,
UART_DATABITS_7=2,
UART_DATABITS_8=3
} UART_DataBits_Type;
typedef enum UART_StopBits_Type {
UART_STOPBITS_1=0,
UART_STOPBITS_1_5=1,
UART_STOPBITS_2=2
} UART_StopBits_Type;
typedef enum UART_Parity_Type {
UART_PARITY_NONE=0,
UART_PARITY_ODD=1,
UART_PARITY_EVEN=2
} UART_Parity_Type;
typedef enum BL_Fun_Type {
DISABLE=0,
ENABLE=1
} BL_Fun_Type;
typedef enum UART_ByteBitInverse_Type {
UART_LSB_FIRST=0,
UART_MSB_FIRST=1
} UART_ByteBitInverse_Type;
struct UART_CFG_Type {
uint32_t uartClk;
uint32_t baudRate;
enum UART_DataBits_Type dataBits;
enum UART_StopBits_Type stopBits;
enum UART_Parity_Type parity;
enum BL_Fun_Type ctsFlowControl;
enum BL_Fun_Type rxDeglitch;
enum BL_Fun_Type rtsSoftwareControl;
enum UART_ByteBitInverse_Type byteBitInverse;
undefined field9_0xf;
};
typedef struct UART_FifoCfg_Type UART_FifoCfg_Type, *PUART_FifoCfg_Type;
struct UART_FifoCfg_Type {
uint8_t txFifoDmaThreshold;
uint8_t rxFifoDmaThreshold;
enum BL_Fun_Type txFifoDmaEnable;
enum BL_Fun_Type rxFifoDmaEnable;
};
typedef enum UART_ID_Type {
UART0_ID=0,
UART1_ID=1,
UART_ID_MAX=2
} UART_ID_Type;
typedef enum UART_AutoBaudDetection_Type {
UART_AUTOBAUD_0X55=0,
UART_AUTOBAUD_STARTBIT=1
} UART_AutoBaudDetection_Type;
typedef enum UART_Direction_Type {
UART_TX=0,
UART_RX=1,
UART_TXRX=2
} UART_Direction_Type;
typedef enum UART_Overflow_Type {
UART_TX_OVERFLOW=0,
UART_TX_UNDERFLOW=1,
UART_RX_OVERFLOW=2,
UART_RX_UNDERFLOW=3
} UART_Overflow_Type;
typedef struct UART_IrCfg_Type UART_IrCfg_Type, *PUART_IrCfg_Type;
struct UART_IrCfg_Type {
enum BL_Fun_Type txIrEnable;
enum BL_Fun_Type rxIrEnable;
enum BL_Fun_Type txIrInverse;
enum BL_Fun_Type rxIrInverse;
uint16_t txIrPulseStart;
uint16_t txIrPulseStop;
uint16_t rxIrPulseStart;
};
typedef enum UART_INT_Type {
UART_INT_TX_END=0,
UART_INT_RX_END=1,
UART_INT_TX_FIFO_REQ=2,
UART_INT_RX_FIFO_REQ=3,
UART_INT_RTO=4,
UART_INT_PCE=5,
UART_INT_TX_FER=6,
UART_INT_RX_FER=7,
UART_INT_ALL=8
} UART_INT_Type;
typedef enum flag {
FL_UPPER=-128,
FL_ZERO=1,
FL_MINUS=2,
FL_PLUS=4,
FL_TICK=8,
FL_SPACE=16,
FL_HASH=32,
FL_SIGNED=64
} flag;
typedef enum ranks {
rank_char=-2,
rank_short=-1,
rank_int=0,
rank_long=1,
rank_longlong=2
} ranks;
typedef enum anon_enum_8.conflictaf6e {
st_normal=0,
st_flags=1,
st_width=2,
st_prec=3,
st_modifiers=4
} anon_enum_8.conflictaf6e;
typedef void * __gnuc_va_list;
typedef __gnuc_va_list va_list;
typedef struct pHidSdio_RegMap_t pHidSdio_RegMap_t, *PpHidSdio_RegMap_t;
struct pHidSdio_RegMap_t {
uint8_t HostToCardEvent;
uint8_t HostIntCause;
uint8_t HostIntMask;
uint8_t HostIntStatus;
uint16_t RdBitMap;
uint16_t WrBitMap;
uint16_t RdLen[16];
uint8_t HostTransferStatus;
uint8_t reserved1[7];
uint8_t CardToHostEvent;
uint8_t reserved2[3];
uint8_t CardIntMask;
uint8_t reserved3[3];
uint8_t CardIntStatus;
uint8_t reserved4[3];
uint8_t CardIntMode;
uint8_t reserved5[3];
uint32_t SqReadBase;
uint32_t SqWriteBase;
uint8_t RdIdx;
uint8_t WrIdx;
uint8_t DnldQueueWrPtr;
uint8_t UpldQueueWrPtr;
uint8_t DnldQueue[8];
uint8_t UpldQueue[8];
uint8_t ChipRev;
uint8_t reserved6;
uint8_t IPRev0;
uint8_t IPRev1;
uint8_t reserved7[4];
uint16_t Scratch2;
uint16_t Scratch1;
uint8_t Ocr0;
uint8_t Ocr1;
uint8_t Ocr2;
uint8_t Config;
uint32_t Config2;
uint32_t Debug;
uint32_t DmaAddr;
uint8_t IoPort[3];
};
typedef struct anon_struct.conflicta49b anon_struct.conflicta49b, *Panon_struct.conflicta49b;
struct anon_struct.conflicta49b {
uint8_t HostToCardEvent;
uint8_t HostIntCause;
uint8_t HostIntMask;
uint8_t HostIntStatus;
uint16_t RdBitMap;
uint16_t WrBitMap;
uint16_t RdLen[16];
uint8_t HostTransferStatus;
uint8_t reserved1[7];
uint8_t CardToHostEvent;
uint8_t reserved2[3];
uint8_t CardIntMask;
uint8_t reserved3[3];
uint8_t CardIntStatus;
uint8_t reserved4[3];
uint8_t CardIntMode;
uint8_t reserved5[3];
uint32_t SqReadBase;
uint32_t SqWriteBase;
uint8_t RdIdx;
uint8_t WrIdx;
uint8_t DnldQueueWrPtr;
uint8_t UpldQueueWrPtr;
uint8_t DnldQueue[8];
uint8_t UpldQueue[8];
uint8_t ChipRev;
uint8_t reserved6;
uint8_t IPRev0;
uint8_t IPRev1;
uint8_t reserved7[4];
uint16_t Scratch2;
uint16_t Scratch1;
uint8_t Ocr0;
uint8_t Ocr1;
uint8_t Ocr2;
uint8_t Config;
uint32_t Config2;
uint32_t Debug;
uint32_t DmaAddr;
uint8_t IoPort[3];
};
typedef enum SDIO_CMD_TYPE {
IOCTL_GET_CONFIG=0,
IOCTL_HID_GET_BLOCK_SIZE=1
} SDIO_CMD_TYPE;
typedef struct Efuse_Ldo11VoutSelTrim_Info_Type Efuse_Ldo11VoutSelTrim_Info_Type, *PEfuse_Ldo11VoutSelTrim_Info_Type;
struct Efuse_Ldo11VoutSelTrim_Info_Type {
uint32_t sel_value:4;
uint32_t parity:1;
uint32_t en:1;
uint32_t rsvd:26;
};
typedef struct Efuse_TxPower_Info_Type Efuse_TxPower_Info_Type, *PEfuse_TxPower_Info_Type;
struct Efuse_TxPower_Info_Type {
uint32_t txpower:5;
uint32_t parity:1;
uint32_t en:1;
uint32_t rsvd:25;
};
typedef struct Efuse_Ana_RC32M_Trim_Type Efuse_Ana_RC32M_Trim_Type, *PEfuse_Ana_RC32M_Trim_Type;
struct Efuse_Ana_RC32M_Trim_Type {
uint32_t trimRc32mCodeFrExt:8;
uint32_t trimRc32mCodeFrExtParity:1;
uint32_t trimRc32mExtCodeEn:1;
uint32_t reserved:22;
};
typedef struct Efuse_Ana_RC32K_Trim_Type Efuse_Ana_RC32K_Trim_Type, *PEfuse_Ana_RC32K_Trim_Type;
struct Efuse_Ana_RC32K_Trim_Type {
uint32_t trimRc32kCodeFrExt:10;
uint32_t trimRc32kCodeFrExtParity:1;
uint32_t trimRc32kExtCodeEn:1;
uint32_t reserved:20;
};
typedef struct Efuse_Capcode_Info_Type Efuse_Capcode_Info_Type, *PEfuse_Capcode_Info_Type;
struct Efuse_Capcode_Info_Type {
uint32_t capCode:6;
uint32_t parity:1;
uint32_t en:1;
uint32_t rsvd:24;
};
typedef enum EF_Ctrl_Sign_Type {
EF_CTRL_SIGN_NONE=0,
EF_CTRL_SIGN_RSA=1,
EF_CTRL_SIGN_ECC=2
} EF_Ctrl_Sign_Type;
typedef struct Efuse_Device_Info_Type Efuse_Device_Info_Type, *PEfuse_Device_Info_Type;
struct Efuse_Device_Info_Type {
uint32_t rsvd:22;
uint32_t customerID:2;
uint32_t rsvd_info:3;
uint32_t memoryInfo:2;
uint32_t coreInfo:1;
uint32_t mcuInfo:1;
uint32_t pinInfo:1;
};
typedef struct Efuse_TSEN_Refcode_Corner_Type Efuse_TSEN_Refcode_Corner_Type, *PEfuse_TSEN_Refcode_Corner_Type;
struct Efuse_TSEN_Refcode_Corner_Type {
uint32_t tsenRefcodeCorner:12;
uint32_t tsenRefcodeCornerParity:1;
uint32_t tsenRefcodeCornerEn:1;
uint32_t tsenRefcodeCornerVersion:1;
uint32_t reserved:17;
};
typedef enum EF_Ctrl_SF_AES_Type {
EF_CTRL_SF_AES_NONE=0,
EF_CTRL_SF_AES_128=1,
EF_CTRL_SF_AES_192=2,
EF_CTRL_SF_AES_256=3
} EF_Ctrl_SF_AES_Type;
typedef struct Efuse_ADC_Gain_Coeff_Type Efuse_ADC_Gain_Coeff_Type, *PEfuse_ADC_Gain_Coeff_Type;
struct Efuse_ADC_Gain_Coeff_Type {
uint32_t adcGainCoeff:12;
uint32_t adcGainCoeffParity:1;
uint32_t adcGainCoeffEn:1;
uint32_t reserved:18;
};
typedef struct EF_Ctrl_Sec_Param_Type EF_Ctrl_Sec_Param_Type, *PEF_Ctrl_Sec_Param_Type;
typedef enum EF_Ctrl_Dbg_Mode_Type {
EF_CTRL_DBG_OPEN=0,
EF_CTRL_DBG_PASSWORD=1,
EF_CTRL_DBG_CLOSE=4
} EF_Ctrl_Dbg_Mode_Type;
struct EF_Ctrl_Sec_Param_Type {
enum EF_Ctrl_Dbg_Mode_Type ef_dbg_mode;
uint8_t ef_dbg_jtag_0_dis;
uint8_t ef_sboot_en;
uint8_t ef_no_hd_boot_en;
};
typedef struct SFlash_Sec_Reg_Cfg SFlash_Sec_Reg_Cfg, *PSFlash_Sec_Reg_Cfg;
struct SFlash_Sec_Reg_Cfg {
uint8_t eraseCmd;
uint8_t programCmd;
uint8_t readCmd;
uint8_t enterSecOptCmd;
uint8_t exitSecOptCmd;
uint8_t blockNum;
undefined field6_0x6;
undefined field7_0x7;
uint8_t * data;
uint32_t addr;
uint32_t len;
};
typedef enum xz_mode {
XZ_SINGLE=0,
XZ_PREALLOC=1,
XZ_DYNALLOC=2
} xz_mode;
typedef enum xz_ret {
XZ_OK=0,
XZ_STREAM_END=1,
XZ_UNSUPPORTED_CHECK=2,
XZ_MEM_ERROR=3,
XZ_MEMLIMIT_ERROR=4,
XZ_FORMAT_ERROR=5,
XZ_OPTIONS_ERROR=6,
XZ_DATA_ERROR=7,
XZ_BUF_ERROR=8
} xz_ret;
typedef struct xz_buf xz_buf, *Pxz_buf;
struct xz_buf {
uint8_t * in;
size_t in_pos;
size_t in_size;
uint8_t * out;
size_t out_pos;
size_t out_size;
};
typedef enum xz_check {
XZ_CHECK_NONE=0,
XZ_CHECK_CRC32=1,
XZ_CHECK_CRC64=4,
XZ_CHECK_SHA256=10
} xz_check;
typedef ulonglong uint64_t;
typedef uint64_t vli_type;
typedef struct GLB_GPIO_Cfg_Type GLB_GPIO_Cfg_Type, *PGLB_GPIO_Cfg_Type;
struct GLB_GPIO_Cfg_Type {
uint8_t gpioPin;
uint8_t gpioFun;
uint8_t gpioMode;
uint8_t pullType;
uint8_t drive;
uint8_t smtCtrl;
};
typedef enum GLB_GPIO_FUNC_Type {
GPIO_FUN_SDIO=1,
GPIO_FUN_FLASH=2,
GPIO_FUN_SPI=4,
GPIO_FUN_I2C=6,
GPIO_FUN_UART=7,
GPIO_FUN_PWM=8,
GPIO_FUN_EXT_PA=9,
GPIO_FUN_ANALOG=10,
GPIO_FUN_SWGPIO=11,
GPIO_FUN_JTAG=14
} GLB_GPIO_FUNC_Type;
typedef enum GLB_GPIO_Type {
GLB_GPIO_PIN_0=0,
GLB_GPIO_PIN_1=1,
GLB_GPIO_PIN_2=2,
GLB_GPIO_PIN_3=3,
GLB_GPIO_PIN_4=4,
GLB_GPIO_PIN_5=5,
GLB_GPIO_PIN_6=6,
GLB_GPIO_PIN_7=7,
GLB_GPIO_PIN_8=8,
GLB_GPIO_PIN_9=9,
GLB_GPIO_PIN_10=10,
GLB_GPIO_PIN_11=11,
GLB_GPIO_PIN_12=12,
GLB_GPIO_PIN_13=13,
GLB_GPIO_PIN_14=14,
GLB_GPIO_PIN_15=15,
GLB_GPIO_PIN_16=16,
GLB_GPIO_PIN_17=17,
GLB_GPIO_PIN_18=18,
GLB_GPIO_PIN_19=19,
GLB_GPIO_PIN_20=20,
GLB_GPIO_PIN_21=21,
GLB_GPIO_PIN_22=22,
GLB_GPIO_PIN_MAX=23
} GLB_GPIO_Type;
typedef struct sys_clk_cfg_t sys_clk_cfg_t, *Psys_clk_cfg_t;
struct sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t pll_clk;
uint8_t hclk_div;
uint8_t bclk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t rsvd[2];
};
typedef struct boot_clk_cfg_t boot_clk_cfg_t, *Pboot_clk_cfg_t;
struct boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
typedef union anon_union.conflict6ea7 anon_union.conflict6ea7, *Panon_union.conflict6ea7;
union anon_union.conflict6ea7 {
uint32_t segment_cnt;
uint32_t img_len;
};
typedef struct boot_cpu_cfg_t boot_cpu_cfg_t, *Pboot_cpu_cfg_t;
struct boot_cpu_cfg_t {
uint32_t bootenable;
uint32_t boot_magic;
uint32_t flash_boot_offset;
uint32_t msp_store_addr;
uint32_t pc_store_addr;
uint32_t dbg_info_addr;
uint32_t dbg_log_addr;
uint32_t dbg_exception_log_addr;
uint32_t pkhash_src;
};
typedef struct boot_flash_cfg_t boot_flash_cfg_t, *Pboot_flash_cfg_t;
struct boot_flash_cfg_t {
uint32_t magiccode;
struct SPI_Flash_Cfg_Type cfg;
uint32_t crc32;
};
typedef union anon_union.conflict6e83 anon_union.conflict6e83, *Panon_union.conflict6e83;
typedef struct anon_struct.conflict6da8 anon_struct.conflict6da8, *Panon_struct.conflict6da8;
struct anon_struct.conflict6da8 {
uint32_t sign:2;
uint32_t encrypt_type:2;
uint32_t key_sel:2;
uint32_t rsvd6_7:2;
uint32_t no_segment:1;
uint32_t cache_select:1;
uint32_t notload_in_bootrom:1;
uint32_t aes_region_lock:1;
uint32_t cache_way_disable:4;
uint32_t crc_ignore:1;
uint32_t hash_ignore:1;
uint32_t halt_ap:1;
uint32_t rsvd19_31:13;
};
union anon_union.conflict6e83 {
struct anon_struct.conflict6da8 bval;
uint32_t wval;
};
typedef struct image_cfg_t image_cfg_t, *Pimage_cfg_t;
typedef union anon_union.conflict6ea7_for_img_segment_info anon_union.conflict6ea7_for_img_segment_info, *Panon_union.conflict6ea7_for_img_segment_info;
typedef union anon_union.conflict6eca_for_img_start anon_union.conflict6eca_for_img_start, *Panon_union.conflict6eca_for_img_start;
union anon_union.conflict6ea7_for_img_segment_info {
uint32_t segment_cnt;
uint32_t img_len;
};
union anon_union.conflict6eca_for_img_start {
uint32_t ramaddr;
uint32_t flashoffset;
};
struct image_cfg_t {
uint8_t encrypt_type;
uint8_t sign_type;
uint8_t key_sel;
uint8_t img_valid;
uint8_t no_segment;
uint8_t cache_select;
uint8_t cache_way_disable;
uint8_t hash_ignore;
uint8_t aes_region_lock;
uint8_t halt_ap;
uint8_t r[2];
union anon_union.conflict6ea7_for_img_segment_info img_segment_info;
uint32_t mspval;
uint32_t entrypoint;
union anon_union.conflict6eca_for_img_start img_start;
uint32_t sig_len;
uint32_t sig_len2;
uint32_t deallen;
uint32_t maxinputlen;
};
typedef union anon_union.conflict6eca anon_union.conflict6eca, *Panon_union.conflict6eca;
union anon_union.conflict6eca {
uint32_t ramaddr;
uint32_t flashoffset;
};
typedef struct bootheader_t bootheader_t, *Pbootheader_t;
typedef union anon_union.conflict6e83_for_bootcfg anon_union.conflict6e83_for_bootcfg, *Panon_union.conflict6e83_for_bootcfg;
union anon_union.conflict6e83_for_bootcfg {
struct anon_struct.conflict6da8 bval;
uint32_t wval;
};
struct bootheader_t {
uint32_t magiccode;
uint32_t rivison;
struct boot_flash_cfg_t flashCfg;
struct boot_clk_cfg_t clkCfg;
union anon_union.conflict6e83_for_bootcfg bootcfg;
union anon_union.conflict6ea7_for_img_segment_info img_segment_info;
uint32_t bootentry;
union anon_union.conflict6eca_for_img_start img_start;
uint8_t hash[32];
uint32_t rsv1;
uint32_t rsv2;
uint32_t crc32;
};
typedef struct PDS_CTL2_Type PDS_CTL2_Type, *PPDS_CTL2_Type;
struct PDS_CTL2_Type {
uint32_t forceCpuPwrOff:1;
uint32_t rsv1:1;
uint32_t forceWbPwrOff:1;
uint32_t rsv3:1;
uint32_t forceCpuIsoPwrOff:1;
uint32_t rsv5:1;
uint32_t forceWbIsoPwrOff:1;
uint32_t rsv7:1;
uint32_t forceCpuPdsRst:1;
uint32_t rsv9:1;
uint32_t forceWbPdsRst:1;
uint32_t rsv11:1;
uint32_t forceCpuMemStby:1;
uint32_t rsv13:1;
uint32_t forceWbMemStby:1;
uint32_t rsv15:1;
uint32_t forceCpuGateClk:1;
uint32_t rsv17:1;
uint32_t forceWbGateClk:1;
uint32_t rsv19_31:12;
};
typedef enum PDS_PLL_CLK_Type {
PDS_PLL_CLK_480M=0,
PDS_PLL_CLK_240M=1,
PDS_PLL_CLK_192M=2,
PDS_PLL_CLK_160M=3,
PDS_PLL_CLK_120M=4,
PDS_PLL_CLK_96M=5,
PDS_PLL_CLK_80M=6,
PDS_PLL_CLK_48M=7,
PDS_PLL_CLK_32M=8
} PDS_PLL_CLK_Type;
typedef struct PDS_DEFAULT_LV_CFG_Type PDS_DEFAULT_LV_CFG_Type, *PPDS_DEFAULT_LV_CFG_Type;
typedef struct PDS_CTL_Type PDS_CTL_Type, *PPDS_CTL_Type;
typedef struct PDS_CTL3_Type PDS_CTL3_Type, *PPDS_CTL3_Type;
typedef struct PDS_CTL4_Type PDS_CTL4_Type, *PPDS_CTL4_Type;
struct PDS_CTL4_Type {
uint32_t cpuPwrOff:1;
uint32_t cpuRst:1;
uint32_t cpuMemStby:1;
uint32_t cpuGateClk:1;
uint32_t rsv4_11:8;
uint32_t WbPwrOff:1;
uint32_t WbRst:1;
uint32_t WbMemStby:1;
uint32_t WbGateClk:1;
uint32_t rsv16_23:8;
uint32_t MiscPwrOff:1;
uint32_t MiscRst:1;
uint32_t MiscMemStby:1;
uint32_t MiscGateClk:1;
uint32_t rsv28_31:4;
};
struct PDS_CTL3_Type {
uint32_t rsv0:1;
uint32_t forceMiscPwrOff:1;
uint32_t rsv2_3:2;
uint32_t forceMiscIsoEn:1;
uint32_t rsv5_6:2;
uint32_t forceMiscPdsRst:1;
uint32_t rsv8_9:2;
uint32_t forceMiscMemStby:1;
uint32_t rsv11_12:2;
uint32_t forceMiscGateClk:1;
uint32_t rsv14_23:10;
uint32_t CpuIsoEn:1;
uint32_t rsv25_26:2;
uint32_t WbIsoEn:1;
uint32_t rsv28_29:2;
uint32_t MiscIsoEn:1;
uint32_t rsv31:1;
};
struct PDS_CTL_Type {
uint32_t pdsStart:1;
uint32_t sleepForever:1;
uint32_t xtalForceOff:1;
uint32_t saveWiFiState:1;
uint32_t dcdc18Off:1;
uint32_t bgSysOff:1;
uint32_t rsv6_7:2;
uint32_t clkOff:1;
uint32_t memStby:1;
uint32_t rsv10:1;
uint32_t isolation:1;
uint32_t waitXtalRdy:1;
uint32_t pdsPwrOff:1;
uint32_t xtalOff:1;
uint32_t socEnbForceOn:1;
uint32_t pdsRstSocEn:1;
uint32_t pdsRC32mOn:1;
uint32_t pdsLdoVselEn:1;
uint32_t rsv19_20:2;
uint32_t wfiMask:1;
uint32_t ldo11Off:1;
uint32_t rsv23:1;
uint32_t pdsLdoVol:4;
uint32_t pdsCtlRfSel:2;
uint32_t pdsCtlPllSel:2;
};
struct PDS_DEFAULT_LV_CFG_Type {
struct PDS_CTL_Type pdsCtl;
struct PDS_CTL2_Type pdsCtl2;
struct PDS_CTL3_Type pdsCtl3;
struct PDS_CTL4_Type pdsCtl4;
};
typedef struct PDS_RAM_CFG_Type PDS_RAM_CFG_Type, *PPDS_RAM_CFG_Type;
struct PDS_RAM_CFG_Type {
uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET:1;
uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET:1;
uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET:1;
uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET:1;
uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_SLP:1;
uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_SLP:1;
uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_SLP:1;
uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_SLP:1;
uint32_t PDS_RAM_CFG_RSV:24;
};
typedef enum PDS_PLL_XTAL_Type {
PDS_PLL_XTAL_NONE=0,
PDS_PLL_XTAL_24M=1,
PDS_PLL_XTAL_32M=2,
PDS_PLL_XTAL_38P4M=3,
PDS_PLL_XTAL_40M=4,
PDS_PLL_XTAL_26M=5,
PDS_PLL_XTAL_RC32M=6
} PDS_PLL_XTAL_Type;
typedef enum HBN_PIR_HPF_Type {
HBN_PIR_HPF_METHOD0=0,
HBN_PIR_HPF_METHOD1=1,
HBN_PIR_HPF_METHOD2=2
} HBN_PIR_HPF_Type;
typedef enum HBN_OUT0_INT_Type {
HBN_OUT0_INT_GPIO7=0,
HBN_OUT0_INT_GPIO8=1,
HBN_OUT0_INT_RTC=2
} HBN_OUT0_INT_Type;
typedef enum HBN_XCLK_CLK_Type {
HBN_XCLK_CLK_RC32M=0,
HBN_XCLK_CLK_XTAL=1
} HBN_XCLK_CLK_Type;
typedef enum HBN_BOR_THRES_Type {
HBN_BOR_THRES_2P0V=0,
HBN_BOR_THRES_2P4V=1
} HBN_BOR_THRES_Type;
typedef struct HBN_APP_CFG_Type HBN_APP_CFG_Type, *PHBN_APP_CFG_Type;
typedef enum HBN_GPIO_INT_Trigger_Type {
HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE=0,
HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE=1,
HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL=2,
HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL=3,
HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE=4,
HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE=5,
HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL=6,
HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL=7
} HBN_GPIO_INT_Trigger_Type;
typedef enum HBN_LEVEL_Type {
HBN_LEVEL_0=0,
HBN_LEVEL_1=1,
HBN_LEVEL_2=2,
HBN_LEVEL_3=3
} HBN_LEVEL_Type;
typedef enum HBN_LDO_LEVEL_Type {
HBN_LDO_LEVEL_0P60V=0,
HBN_LDO_LEVEL_0P65V=1,
HBN_LDO_LEVEL_0P70V=2,
HBN_LDO_LEVEL_0P75V=3,
HBN_LDO_LEVEL_0P80V=4,
HBN_LDO_LEVEL_0P85V=5,
HBN_LDO_LEVEL_0P90V=6,
HBN_LDO_LEVEL_0P95V=7,
HBN_LDO_LEVEL_1P00V=8,
HBN_LDO_LEVEL_1P05V=9,
HBN_LDO_LEVEL_1P10V=10,
HBN_LDO_LEVEL_1P15V=11,
HBN_LDO_LEVEL_1P20V=12,
HBN_LDO_LEVEL_1P25V=13,
HBN_LDO_LEVEL_1P30V=14,
HBN_LDO_LEVEL_1P35V=15
} HBN_LDO_LEVEL_Type;
struct HBN_APP_CFG_Type {
uint8_t useXtal32k;
undefined field1_0x1;
undefined field2_0x2;
undefined field3_0x3;
uint32_t sleepTime;
uint8_t gpioWakeupSrc;
enum HBN_GPIO_INT_Trigger_Type gpioTrigType;
undefined field7_0xa;
undefined field8_0xb;
struct SPI_Flash_Cfg_Type * flashCfg;
enum HBN_LEVEL_Type hbnLevel;
enum HBN_LDO_LEVEL_Type ldoLevel;
undefined field12_0x12;
undefined field13_0x13;
};
typedef struct HBN_BOR_CFG_Type HBN_BOR_CFG_Type, *PHBN_BOR_CFG_Type;
struct HBN_BOR_CFG_Type {
uint8_t enableBor;
uint8_t enableBorInt;
uint8_t borThreshold;
uint8_t enablePorInBor;
};
typedef enum HBN_PIR_LPF_Type {
HBN_PIR_LPF_DIV1=0,
HBN_PIR_LPF_DIV2=1
} HBN_PIR_LPF_Type;
typedef struct HBN_PIR_INT_CFG_Type HBN_PIR_INT_CFG_Type, *PHBN_PIR_INT_CFG_Type;
struct HBN_PIR_INT_CFG_Type {
enum BL_Fun_Type lowIntEn;
enum BL_Fun_Type highIntEn;
};
typedef enum HBN_32K_CLK_Type {
HBN_32K_RC=0,
HBN_32K_XTAL=1,
HBN_32K_DIG=3
} HBN_32K_CLK_Type;
typedef enum HBN_ROOT_CLK_Type {
HBN_ROOT_CLK_RC32M=0,
HBN_ROOT_CLK_XTAL=1,
HBN_ROOT_CLK_PLL=2
} HBN_ROOT_CLK_Type;
typedef enum HBN_UART_CLK_Type {
HBN_UART_CLK_FCLK=0,
HBN_UART_CLK_160M=1
} HBN_UART_CLK_Type;
typedef enum HBN_INT_Type {
HBN_INT_GPIO7=0,
HBN_INT_GPIO8=1,
HBN_INT_RTC=16,
HBN_INT_PIR=17,
HBN_INT_BOR=18,
HBN_INT_ACOMP0=20,
HBN_INT_ACOMP1=22
} HBN_INT_Type;
typedef enum HBN_OUT1_INT_Type {
HBN_OUT1_INT_PIR=0,
HBN_OUT1_INT_BOR=1,
HBN_OUT1_INT_ACOMP0=2,
HBN_OUT1_INT_ACOMP1=3
} HBN_OUT1_INT_Type;
typedef enum HBN_ACOMP_INT_EDGE_Type {
HBN_ACOMP_INT_EDGE_POSEDGE=0,
HBN_ACOMP_INT_EDGE_NEGEDGE=1
} HBN_ACOMP_INT_EDGE_Type;
typedef enum HBN_BOR_MODE_Type {
HBN_BOR_MODE_POR_INDEPENDENT=0,
HBN_BOR_MODE_POR_RELEVANT=1
} HBN_BOR_MODE_Type;
typedef enum HBN_RTC_INT_Delay_Type {
HBN_RTC_INT_DELAY_32T=0,
HBN_RTC_INT_DELAY_0T=1
} HBN_RTC_INT_Delay_Type;
typedef enum BL_Mask_Type {
UNMASK=0,
MASK=1
} BL_Mask_Type;
typedef enum BL_Sts_Type {
RESET=0,
SET=1
} BL_Sts_Type;
typedef enum BL_Err_Type {
SUCCESS=0,
ERROR=1,
TIMEOUT=2
} BL_Err_Type;
typedef enum anon_enum_8.conflicta8 {
BL_AHB_SLAVE1_GLB=0,
DISABLE=0,