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deps: V8: cherry-pick ed3eedae33d0
Original commit message: Merged: [ia32][wasm-simd] Fix aligned moves in codegen For SIMD instructions that use aligned moves (like movaps or movapd), we don't have correct memory alignment for SIMD moves yet. Switch to to movupd. TBR=bbudge@chromium.org,adamk@chromium.org Bug: v8:9198 Bug: v8:10831 Bug: chromium:1134039 (cherry picked from commit ab23ff3c0eed141361365241d13e3211efd608cf) Change-Id: Icc038b4a32364b8bc66b723403ccc11f954b080d No-Try: true No-Presubmit: true No-Tree-Checks: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2469600 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/branch-heads/8.6@{#30} Cr-Branched-From: a64aed2333abf49e494d2a5ce24bbd14fff19f60-refs/heads/8.6.395@{#1} Cr-Branched-From: a626bc036236c9bf92ac7b87dc40c9e538b087e3-refs/heads/master@{#69472} Refs: v8/v8@ed3eeda PR-URL: #38275 Reviewed-By: Matteo Collina <matteo.collina@gmail.com> Reviewed-By: Jiawen Geng <technicalcute@gmail.com> Reviewed-By: Shelley Vohr <codebytere@gmail.com>
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+22
-5
lines changed

6 files changed

+22
-5
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common.gypi

+1-1
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@
3636

3737
# Reset this number to 0 on major V8 upgrades.
3838
# Increment by one for each non-official patch applied to deps/v8.
39-
'v8_embedder_string': '-node.35',
39+
'v8_embedder_string': '-node.36',
4040

4141
##### V8 defaults for Node.js #####
4242

deps/v8/src/codegen/ia32/assembler-ia32.h

+4
Original file line numberDiff line numberDiff line change
@@ -959,6 +959,9 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
959959
void movapd(XMMRegister dst, Operand src) {
960960
sse2_instr(dst, src, 0x66, 0x0F, 0x28);
961961
}
962+
void movupd(XMMRegister dst, Operand src) {
963+
sse2_instr(dst, src, 0x66, 0x0F, 0x10);
964+
}
962965

963966
void movmskpd(Register dst, XMMRegister src);
964967
void movmskps(Register dst, XMMRegister src);
@@ -1331,6 +1334,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
13311334
void vmovapd(XMMRegister dst, Operand src) { vpd(0x28, dst, xmm0, src); }
13321335
void vmovups(XMMRegister dst, XMMRegister src) { vmovups(dst, Operand(src)); }
13331336
void vmovups(XMMRegister dst, Operand src) { vps(0x10, dst, xmm0, src); }
1337+
void vmovupd(XMMRegister dst, Operand src) { vpd(0x10, dst, xmm0, src); }
13341338
void vshufps(XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) {
13351339
vshufps(dst, src1, Operand(src2), imm8);
13361340
}

deps/v8/src/codegen/ia32/macro-assembler-ia32.h

+1
Original file line numberDiff line numberDiff line change
@@ -292,6 +292,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
292292
AVX_OP2_WITH_TYPE(Movaps, movaps, XMMRegister, XMMRegister)
293293
AVX_OP2_WITH_TYPE(Movapd, movapd, XMMRegister, XMMRegister)
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AVX_OP2_WITH_TYPE(Movapd, movapd, XMMRegister, const Operand&)
295+
AVX_OP2_WITH_TYPE(Movupd, movupd, XMMRegister, const Operand&)
295296
AVX_OP2_WITH_TYPE(Pmovmskb, pmovmskb, Register, XMMRegister)
296297
AVX_OP2_WITH_TYPE(Movmskps, movmskps, Register, XMMRegister)
297298

deps/v8/src/compiler/backend/ia32/code-generator-ia32.cc

+3-3
Original file line numberDiff line numberDiff line change
@@ -1966,7 +1966,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
19661966
tmp = i.TempSimd128Register(0);
19671967
// The minpd instruction doesn't propagate NaNs and +0's in its first
19681968
// operand. Perform minpd in both orders, merge the resuls, and adjust.
1969-
__ Movapd(tmp, src1);
1969+
__ Movupd(tmp, src1);
19701970
__ Minpd(tmp, tmp, src);
19711971
__ Minpd(dst, src, src1);
19721972
// propagate -0's and NaNs, which may be non-canonical.
@@ -1985,7 +1985,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
19851985
tmp = i.TempSimd128Register(0);
19861986
// The maxpd instruction doesn't propagate NaNs and +0's in its first
19871987
// operand. Perform maxpd in both orders, merge the resuls, and adjust.
1988-
__ Movapd(tmp, src1);
1988+
__ Movupd(tmp, src1);
19891989
__ Maxpd(tmp, tmp, src);
19901990
__ Maxpd(dst, src, src1);
19911991
// Find discrepancies.
@@ -2375,7 +2375,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
23752375
XMMRegister dst = i.OutputSimd128Register();
23762376
Operand src1 = i.InputOperand(1);
23772377
// See comment above for correction of maxps.
2378-
__ movaps(kScratchDoubleReg, src1);
2378+
__ vmovups(kScratchDoubleReg, src1);
23792379
__ vmaxps(kScratchDoubleReg, kScratchDoubleReg, dst);
23802380
__ vmaxps(dst, dst, src1);
23812381
__ vxorps(dst, dst, kScratchDoubleReg);

deps/v8/src/diagnostics/ia32/disasm-ia32.cc

+11-1
Original file line numberDiff line numberDiff line change
@@ -1161,6 +1161,10 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
11611161
int mod, regop, rm, vvvv = vex_vreg();
11621162
get_modrm(*current, &mod, &regop, &rm);
11631163
switch (opcode) {
1164+
case 0x10:
1165+
AppendToBuffer("vmovupd %s,", NameOfXMMRegister(regop));
1166+
current += PrintRightXMMOperand(current);
1167+
break;
11641168
case 0x28:
11651169
AppendToBuffer("vmovapd %s,", NameOfXMMRegister(regop));
11661170
current += PrintRightXMMOperand(current);
@@ -2090,7 +2094,13 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
20902094
data += 2;
20912095
} else if (*data == 0x0F) {
20922096
data++;
2093-
if (*data == 0x28) {
2097+
if (*data == 0x10) {
2098+
data++;
2099+
int mod, regop, rm;
2100+
get_modrm(*data, &mod, &regop, &rm);
2101+
AppendToBuffer("movupd %s,", NameOfXMMRegister(regop));
2102+
data += PrintRightXMMOperand(data);
2103+
} else if (*data == 0x28) {
20942104
data++;
20952105
int mod, regop, rm;
20962106
get_modrm(*data, &mod, &regop, &rm);

deps/v8/test/cctest/test-disasm-ia32.cc

+2
Original file line numberDiff line numberDiff line change
@@ -473,6 +473,7 @@ TEST(DisasmIa320) {
473473

474474
__ movapd(xmm0, xmm1);
475475
__ movapd(xmm0, Operand(edx, 4));
476+
__ movupd(xmm0, Operand(edx, 4));
476477

477478
__ movd(xmm0, edi);
478479
__ movd(xmm0, Operand(ebx, ecx, times_4, 10000));
@@ -689,6 +690,7 @@ TEST(DisasmIa320) {
689690
__ vmovaps(xmm0, xmm1);
690691
__ vmovapd(xmm0, xmm1);
691692
__ vmovapd(xmm0, Operand(ebx, ecx, times_4, 10000));
693+
__ vmovupd(xmm0, Operand(ebx, ecx, times_4, 10000));
692694
__ vshufps(xmm0, xmm1, xmm2, 3);
693695
__ vshufps(xmm0, xmm1, Operand(edx, 4), 3);
694696
__ vhaddps(xmm0, xmm1, xmm2);

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