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Re-run update.sh
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888 files changed

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‎src/inner/accessctrl/adc0.rs

-8
Original file line numberDiff line numberDiff line change
@@ -79,49 +79,41 @@ impl R {
7979
impl W {
8080
#[doc = "Bit 0 - If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
8181
#[inline(always)]
82-
#[must_use]
8382
pub fn nsu(&mut self) -> NSU_W<ADC0_SPEC> {
8483
NSU_W::new(self, 0)
8584
}
8685
#[doc = "Bit 1 - If 1, ADC0 can be accessed from a Non-secure, Privileged context."]
8786
#[inline(always)]
88-
#[must_use]
8987
pub fn nsp(&mut self) -> NSP_W<ADC0_SPEC> {
9088
NSP_W::new(self, 1)
9189
}
9290
#[doc = "Bit 2 - If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."]
9391
#[inline(always)]
94-
#[must_use]
9592
pub fn su(&mut self) -> SU_W<ADC0_SPEC> {
9693
SU_W::new(self, 2)
9794
}
9895
#[doc = "Bit 3 - If 1, ADC0 can be accessed from a Secure, Privileged context."]
9996
#[inline(always)]
100-
#[must_use]
10197
pub fn sp(&mut self) -> SP_W<ADC0_SPEC> {
10298
SP_W::new(self, 3)
10399
}
104100
#[doc = "Bit 4 - If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
105101
#[inline(always)]
106-
#[must_use]
107102
pub fn core0(&mut self) -> CORE0_W<ADC0_SPEC> {
108103
CORE0_W::new(self, 4)
109104
}
110105
#[doc = "Bit 5 - If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
111106
#[inline(always)]
112-
#[must_use]
113107
pub fn core1(&mut self) -> CORE1_W<ADC0_SPEC> {
114108
CORE1_W::new(self, 5)
115109
}
116110
#[doc = "Bit 6 - If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
117111
#[inline(always)]
118-
#[must_use]
119112
pub fn dma(&mut self) -> DMA_W<ADC0_SPEC> {
120113
DMA_W::new(self, 6)
121114
}
122115
#[doc = "Bit 7 - If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
123116
#[inline(always)]
124-
#[must_use]
125117
pub fn dbg(&mut self) -> DBG_W<ADC0_SPEC> {
126118
DBG_W::new(self, 7)
127119
}

‎src/inner/accessctrl/busctrl.rs

-8
Original file line numberDiff line numberDiff line change
@@ -79,49 +79,41 @@ impl R {
7979
impl W {
8080
#[doc = "Bit 0 - If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
8181
#[inline(always)]
82-
#[must_use]
8382
pub fn nsu(&mut self) -> NSU_W<BUSCTRL_SPEC> {
8483
NSU_W::new(self, 0)
8584
}
8685
#[doc = "Bit 1 - If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."]
8786
#[inline(always)]
88-
#[must_use]
8987
pub fn nsp(&mut self) -> NSP_W<BUSCTRL_SPEC> {
9088
NSP_W::new(self, 1)
9189
}
9290
#[doc = "Bit 2 - If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."]
9391
#[inline(always)]
94-
#[must_use]
9592
pub fn su(&mut self) -> SU_W<BUSCTRL_SPEC> {
9693
SU_W::new(self, 2)
9794
}
9895
#[doc = "Bit 3 - If 1, BUSCTRL can be accessed from a Secure, Privileged context."]
9996
#[inline(always)]
100-
#[must_use]
10197
pub fn sp(&mut self) -> SP_W<BUSCTRL_SPEC> {
10298
SP_W::new(self, 3)
10399
}
104100
#[doc = "Bit 4 - If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
105101
#[inline(always)]
106-
#[must_use]
107102
pub fn core0(&mut self) -> CORE0_W<BUSCTRL_SPEC> {
108103
CORE0_W::new(self, 4)
109104
}
110105
#[doc = "Bit 5 - If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
111106
#[inline(always)]
112-
#[must_use]
113107
pub fn core1(&mut self) -> CORE1_W<BUSCTRL_SPEC> {
114108
CORE1_W::new(self, 5)
115109
}
116110
#[doc = "Bit 6 - If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
117111
#[inline(always)]
118-
#[must_use]
119112
pub fn dma(&mut self) -> DMA_W<BUSCTRL_SPEC> {
120113
DMA_W::new(self, 6)
121114
}
122115
#[doc = "Bit 7 - If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
123116
#[inline(always)]
124-
#[must_use]
125117
pub fn dbg(&mut self) -> DBG_W<BUSCTRL_SPEC> {
126118
DBG_W::new(self, 7)
127119
}

‎src/inner/accessctrl/cfgreset.rs

-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@ pub type CFGRESET_W<'a, REG> = crate::BitWriter<'a, REG>;
77
impl W {
88
#[doc = "Bit 0"]
99
#[inline(always)]
10-
#[must_use]
1110
pub fn cfgreset(&mut self) -> CFGRESET_W<CFGRESET_SPEC> {
1211
CFGRESET_W::new(self, 0)
1312
}

‎src/inner/accessctrl/clocks.rs

-8
Original file line numberDiff line numberDiff line change
@@ -79,49 +79,41 @@ impl R {
7979
impl W {
8080
#[doc = "Bit 0 - If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
8181
#[inline(always)]
82-
#[must_use]
8382
pub fn nsu(&mut self) -> NSU_W<CLOCKS_SPEC> {
8483
NSU_W::new(self, 0)
8584
}
8685
#[doc = "Bit 1 - If 1, CLOCKS can be accessed from a Non-secure, Privileged context."]
8786
#[inline(always)]
88-
#[must_use]
8987
pub fn nsp(&mut self) -> NSP_W<CLOCKS_SPEC> {
9088
NSP_W::new(self, 1)
9189
}
9290
#[doc = "Bit 2 - If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."]
9391
#[inline(always)]
94-
#[must_use]
9592
pub fn su(&mut self) -> SU_W<CLOCKS_SPEC> {
9693
SU_W::new(self, 2)
9794
}
9895
#[doc = "Bit 3 - If 1, CLOCKS can be accessed from a Secure, Privileged context."]
9996
#[inline(always)]
100-
#[must_use]
10197
pub fn sp(&mut self) -> SP_W<CLOCKS_SPEC> {
10298
SP_W::new(self, 3)
10399
}
104100
#[doc = "Bit 4 - If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
105101
#[inline(always)]
106-
#[must_use]
107102
pub fn core0(&mut self) -> CORE0_W<CLOCKS_SPEC> {
108103
CORE0_W::new(self, 4)
109104
}
110105
#[doc = "Bit 5 - If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
111106
#[inline(always)]
112-
#[must_use]
113107
pub fn core1(&mut self) -> CORE1_W<CLOCKS_SPEC> {
114108
CORE1_W::new(self, 5)
115109
}
116110
#[doc = "Bit 6 - If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
117111
#[inline(always)]
118-
#[must_use]
119112
pub fn dma(&mut self) -> DMA_W<CLOCKS_SPEC> {
120113
DMA_W::new(self, 6)
121114
}
122115
#[doc = "Bit 7 - If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
123116
#[inline(always)]
124-
#[must_use]
125117
pub fn dbg(&mut self) -> DBG_W<CLOCKS_SPEC> {
126118
DBG_W::new(self, 7)
127119
}

‎src/inner/accessctrl/coresight_periph.rs

-8
Original file line numberDiff line numberDiff line change
@@ -79,49 +79,41 @@ impl R {
7979
impl W {
8080
#[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
8181
#[inline(always)]
82-
#[must_use]
8382
pub fn nsu(&mut self) -> NSU_W<CORESIGHT_PERIPH_SPEC> {
8483
NSU_W::new(self, 0)
8584
}
8685
#[doc = "Bit 1 - If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."]
8786
#[inline(always)]
88-
#[must_use]
8987
pub fn nsp(&mut self) -> NSP_W<CORESIGHT_PERIPH_SPEC> {
9088
NSP_W::new(self, 1)
9189
}
9290
#[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."]
9391
#[inline(always)]
94-
#[must_use]
9592
pub fn su(&mut self) -> SU_W<CORESIGHT_PERIPH_SPEC> {
9693
SU_W::new(self, 2)
9794
}
9895
#[doc = "Bit 3 - If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."]
9996
#[inline(always)]
100-
#[must_use]
10197
pub fn sp(&mut self) -> SP_W<CORESIGHT_PERIPH_SPEC> {
10298
SP_W::new(self, 3)
10399
}
104100
#[doc = "Bit 4 - If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
105101
#[inline(always)]
106-
#[must_use]
107102
pub fn core0(&mut self) -> CORE0_W<CORESIGHT_PERIPH_SPEC> {
108103
CORE0_W::new(self, 4)
109104
}
110105
#[doc = "Bit 5 - If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
111106
#[inline(always)]
112-
#[must_use]
113107
pub fn core1(&mut self) -> CORE1_W<CORESIGHT_PERIPH_SPEC> {
114108
CORE1_W::new(self, 5)
115109
}
116110
#[doc = "Bit 6 - If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
117111
#[inline(always)]
118-
#[must_use]
119112
pub fn dma(&mut self) -> DMA_W<CORESIGHT_PERIPH_SPEC> {
120113
DMA_W::new(self, 6)
121114
}
122115
#[doc = "Bit 7 - If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
123116
#[inline(always)]
124-
#[must_use]
125117
pub fn dbg(&mut self) -> DBG_W<CORESIGHT_PERIPH_SPEC> {
126118
DBG_W::new(self, 7)
127119
}

‎src/inner/accessctrl/coresight_trace.rs

-8
Original file line numberDiff line numberDiff line change
@@ -79,49 +79,41 @@ impl R {
7979
impl W {
8080
#[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
8181
#[inline(always)]
82-
#[must_use]
8382
pub fn nsu(&mut self) -> NSU_W<CORESIGHT_TRACE_SPEC> {
8483
NSU_W::new(self, 0)
8584
}
8685
#[doc = "Bit 1 - If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."]
8786
#[inline(always)]
88-
#[must_use]
8987
pub fn nsp(&mut self) -> NSP_W<CORESIGHT_TRACE_SPEC> {
9088
NSP_W::new(self, 1)
9189
}
9290
#[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."]
9391
#[inline(always)]
94-
#[must_use]
9592
pub fn su(&mut self) -> SU_W<CORESIGHT_TRACE_SPEC> {
9693
SU_W::new(self, 2)
9794
}
9895
#[doc = "Bit 3 - If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."]
9996
#[inline(always)]
100-
#[must_use]
10197
pub fn sp(&mut self) -> SP_W<CORESIGHT_TRACE_SPEC> {
10298
SP_W::new(self, 3)
10399
}
104100
#[doc = "Bit 4 - If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
105101
#[inline(always)]
106-
#[must_use]
107102
pub fn core0(&mut self) -> CORE0_W<CORESIGHT_TRACE_SPEC> {
108103
CORE0_W::new(self, 4)
109104
}
110105
#[doc = "Bit 5 - If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
111106
#[inline(always)]
112-
#[must_use]
113107
pub fn core1(&mut self) -> CORE1_W<CORESIGHT_TRACE_SPEC> {
114108
CORE1_W::new(self, 5)
115109
}
116110
#[doc = "Bit 6 - If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
117111
#[inline(always)]
118-
#[must_use]
119112
pub fn dma(&mut self) -> DMA_W<CORESIGHT_TRACE_SPEC> {
120113
DMA_W::new(self, 6)
121114
}
122115
#[doc = "Bit 7 - If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
123116
#[inline(always)]
124-
#[must_use]
125117
pub fn dbg(&mut self) -> DBG_W<CORESIGHT_TRACE_SPEC> {
126118
DBG_W::new(self, 7)
127119
}

‎src/inner/accessctrl/dma.rs

-8
Original file line numberDiff line numberDiff line change
@@ -79,49 +79,41 @@ impl R {
7979
impl W {
8080
#[doc = "Bit 0 - If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
8181
#[inline(always)]
82-
#[must_use]
8382
pub fn nsu(&mut self) -> NSU_W<DMA_SPEC> {
8483
NSU_W::new(self, 0)
8584
}
8685
#[doc = "Bit 1 - If 1, DMA can be accessed from a Non-secure, Privileged context."]
8786
#[inline(always)]
88-
#[must_use]
8987
pub fn nsp(&mut self) -> NSP_W<DMA_SPEC> {
9088
NSP_W::new(self, 1)
9189
}
9290
#[doc = "Bit 2 - If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."]
9391
#[inline(always)]
94-
#[must_use]
9592
pub fn su(&mut self) -> SU_W<DMA_SPEC> {
9693
SU_W::new(self, 2)
9794
}
9895
#[doc = "Bit 3 - If 1, DMA can be accessed from a Secure, Privileged context."]
9996
#[inline(always)]
100-
#[must_use]
10197
pub fn sp(&mut self) -> SP_W<DMA_SPEC> {
10298
SP_W::new(self, 3)
10399
}
104100
#[doc = "Bit 4 - If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
105101
#[inline(always)]
106-
#[must_use]
107102
pub fn core0(&mut self) -> CORE0_W<DMA_SPEC> {
108103
CORE0_W::new(self, 4)
109104
}
110105
#[doc = "Bit 5 - If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
111106
#[inline(always)]
112-
#[must_use]
113107
pub fn core1(&mut self) -> CORE1_W<DMA_SPEC> {
114108
CORE1_W::new(self, 5)
115109
}
116110
#[doc = "Bit 6 - If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
117111
#[inline(always)]
118-
#[must_use]
119112
pub fn dma(&mut self) -> DMA_W<DMA_SPEC> {
120113
DMA_W::new(self, 6)
121114
}
122115
#[doc = "Bit 7 - If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
123116
#[inline(always)]
124-
#[must_use]
125117
pub fn dbg(&mut self) -> DBG_W<DMA_SPEC> {
126118
DBG_W::new(self, 7)
127119
}

‎src/inner/accessctrl/force_core_ns.rs

-1
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@ impl R {
1616
impl W {
1717
#[doc = "Bit 1"]
1818
#[inline(always)]
19-
#[must_use]
2019
pub fn core1(&mut self) -> CORE1_W<FORCE_CORE_NS_SPEC> {
2120
CORE1_W::new(self, 1)
2221
}

‎src/inner/accessctrl/gpio_nsmask0.rs

-1
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@ impl R {
1616
impl W {
1717
#[doc = "Bits 0:31"]
1818
#[inline(always)]
19-
#[must_use]
2019
pub fn gpio_nsmask0(&mut self) -> GPIO_NSMASK0_W<GPIO_NSMASK0_SPEC> {
2120
GPIO_NSMASK0_W::new(self, 0)
2221
}

‎src/inner/accessctrl/gpio_nsmask1.rs

-6
Original file line numberDiff line numberDiff line change
@@ -61,37 +61,31 @@ impl R {
6161
impl W {
6262
#[doc = "Bits 0:15"]
6363
#[inline(always)]
64-
#[must_use]
6564
pub fn gpio(&mut self) -> GPIO_W<GPIO_NSMASK1_SPEC> {
6665
GPIO_W::new(self, 0)
6766
}
6867
#[doc = "Bit 24"]
6968
#[inline(always)]
70-
#[must_use]
7169
pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_NSMASK1_SPEC> {
7270
USB_DP_W::new(self, 24)
7371
}
7472
#[doc = "Bit 25"]
7573
#[inline(always)]
76-
#[must_use]
7774
pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_NSMASK1_SPEC> {
7875
USB_DM_W::new(self, 25)
7976
}
8077
#[doc = "Bit 26"]
8178
#[inline(always)]
82-
#[must_use]
8379
pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_NSMASK1_SPEC> {
8480
QSPI_SCK_W::new(self, 26)
8581
}
8682
#[doc = "Bit 27"]
8783
#[inline(always)]
88-
#[must_use]
8984
pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_NSMASK1_SPEC> {
9085
QSPI_CSN_W::new(self, 27)
9186
}
9287
#[doc = "Bits 28:31"]
9388
#[inline(always)]
94-
#[must_use]
9589
pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_NSMASK1_SPEC> {
9690
QSPI_SD_W::new(self, 28)
9791
}

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