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1 |
| -// See https://github.com/llvm/llvm-project/blob/d85b94bf0080dcd780656c0f5e6342800720eba9/llvm/lib/Target/CSKY/CSKYCallingConv.td |
2 |
| -use crate::abi::call::{ArgAbi, FnAbi}; |
| 1 | +// Reference: CSKY ABI Manual |
| 2 | +// https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1695027452256/T-HEAD_800_Series_ABI_Standards_Manual.pdf |
| 3 | +// |
| 4 | +// Reference: Clang CSKY lowering code |
| 5 | +// https://github.com/llvm/llvm-project/blob/4a074f32a6914f2a8d7215d78758c24942dddc3d/clang/lib/CodeGen/Targets/CSKY.cpp#L76-L162 |
3 | 6 |
|
4 |
| -fn classify_ret<Ty>(ret: &mut ArgAbi<'_, Ty>) { |
5 |
| - if ret.layout.is_aggregate() || ret.layout.size.bits() > 64 { |
6 |
| - ret.make_indirect(); |
| 7 | +use crate::abi::call::{ArgAbi, FnAbi, Reg, Uniform}; |
| 8 | + |
| 9 | +fn classify_ret<Ty>(arg: &mut ArgAbi<'_, Ty>) { |
| 10 | + // For return type, aggregate which <= 2*XLen will be returned in registers. |
| 11 | + // Otherwise, aggregate will be returned indirectly. |
| 12 | + if arg.layout.is_aggregate() { |
| 13 | + let total = arg.layout.size; |
| 14 | + if total.bits() > 64 { |
| 15 | + arg.make_indirect(); |
| 16 | + } else if total.bits() > 32 { |
| 17 | + arg.cast_to(Uniform { unit: Reg::i32(), total }); |
| 18 | + } else { |
| 19 | + arg.cast_to(Reg::i32()); |
| 20 | + } |
7 | 21 | } else {
|
8 |
| - ret.extend_integer_width_to(32); |
| 22 | + arg.extend_integer_width_to(32); |
9 | 23 | }
|
10 | 24 | }
|
11 | 25 |
|
12 | 26 | fn classify_arg<Ty>(arg: &mut ArgAbi<'_, Ty>) {
|
13 |
| - if arg.layout.is_aggregate() || arg.layout.size.bits() > 64 { |
14 |
| - arg.make_indirect(); |
| 27 | + // For argument type, the first 4*XLen parts of aggregate will be passed |
| 28 | + // in registers, and the rest will be passed in stack. |
| 29 | + // So we can coerce to integers directly and let backend handle it correctly. |
| 30 | + if arg.layout.is_aggregate() { |
| 31 | + let total = arg.layout.size; |
| 32 | + if total.bits() > 32 { |
| 33 | + arg.cast_to(Uniform { unit: Reg::i32(), total }); |
| 34 | + } else { |
| 35 | + arg.cast_to(Reg::i32()); |
| 36 | + } |
15 | 37 | } else {
|
16 | 38 | arg.extend_integer_width_to(32);
|
17 | 39 | }
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