Rollup merge of #72439 - westernmagic:master, r=Amanieu

RalfJung · web-flow · commit 37894559abd6 · 2020-05-29T21:58:34.000+02:00
NVPTX support for new asm! This PR implements the new `asm!` syntax for the `nvptx64-nvidia-cuda` target. r? @Amanieu
diff --git a/src/doc/unstable-book/src/library-features/asm.md b/src/doc/unstable-book/src/library-features/asm.md
@@ -468,12 +468,17 @@ Here is the list of currently supported register classes:
 | ARM | `qreg` | `q[0-15]` | `w` |
 | ARM | `qreg_low8` | `q[0-7]` | `t` |
 | ARM | `qreg_low4` | `q[0-3]` | `x` |
+| NVPTX | `reg16` | None\* | `h` |
+| NVPTX | `reg32` | None\* | `r` |
+| NVPTX | `reg64` | None\* | `l` |
 | RISC-V | `reg` | `x1`, `x[5-7]`, `x[9-15]`, `x[16-31]` (non-RV32E) | `r` |
 | RISC-V | `freg` | `f[0-31]` | `f` |
 
 > **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
 >
 > Note #2: On x86-64 the high byte registers (e.g. `ah`) are only available when used as an explicit register. Specifying the `reg_byte` register class for an operand will always allocate a low byte register.
+>
+> Note #3: NVPTX doesn't have a fixed register set, so named registers are not supported.
 
 Additional register classes may be added in the future based on demand (e.g. MMX, x87, etc).
 
@@ -495,6 +500,9 @@ Each register class has constraints on which value types they can be used with.
 | ARM | `sreg` | `vfp2` | `i32`, `f32` |
 | ARM | `dreg` | `vfp2` | `i64`, `f64`, `i8x8`, `i16x4`, `i32x2`, `i64x1`, `f32x2` |
 | ARM | `qreg` | `neon` | `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4` |
+| NVPTX | `reg16` | None | `i8`, `i16` |
+| NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
+| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
 | RISC-V32 | `reg` | None | `i8`, `i16`, `i32`, `f32` |
 | RISC-V64 | `reg` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
 | RISC-V | `freg` | `f` | `f32` |
@@ -610,6 +618,9 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
 | ARM | `dreg` | None | `d0` | `P` |
 | ARM | `qreg` | None | `q0` | `q` |
 | ARM | `qreg` | `e` / `f` | `d0` / `d1` | `e` / `f` |
+| NVPTX | `reg16` | None | `rs0` | None |
+| NVPTX | `reg32` | None | `r0` | None |
+| NVPTX | `reg64` | None | `rd0` | None |
 | RISC-V | `reg` | None | `x1` | None |
 | RISC-V | `freg` | None | `f0` | None |
 
diff --git a/src/librustc_codegen_llvm/asm.rs b/src/librustc_codegen_llvm/asm.rs
@@ -254,6 +254,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
                     ]);
                 }
                 InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
+                InlineAsmArch::Nvptx64 => {}
             }
         }
         if !options.contains(InlineAsmOptions::NOMEM) {
@@ -410,6 +411,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass) -> String {
             | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
             | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
+            InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
+            InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
+            InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
             InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
             InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f",
             InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",
@@ -452,6 +456,7 @@ fn modifier_to_llvm(
                 modifier
             }
         }
+        InlineAsmRegClass::Nvptx(_) => None,
         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
         | InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
         InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
@@ -502,6 +507,9 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
             cx.type_vector(cx.type_i64(), 2)
         }
+        InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
+        InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
+        InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),
         InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
diff --git a/src/librustc_target/asm/mod.rs b/src/librustc_target/asm/mod.rs
@@ -60,6 +60,7 @@ macro_rules! def_regs {
             #error = [$($bad_reg:literal),+] => $error:literal,
         )*
     }) => {
+        #[allow(unreachable_code)]
         #[derive(Copy, Clone, RustcEncodable, RustcDecodable, Debug, Eq, PartialEq, Hash, HashStable_Generic)]
         #[allow(non_camel_case_types)]
         pub enum $arch_reg {
@@ -102,19 +103,20 @@ macro_rules! def_regs {
         pub(super) fn fill_reg_map(
             _arch: super::InlineAsmArch,
             mut _has_feature: impl FnMut(&str) -> bool,
-            map: &mut rustc_data_structures::fx::FxHashMap<
+            _map: &mut rustc_data_structures::fx::FxHashMap<
                 super::InlineAsmRegClass,
                 rustc_data_structures::fx::FxHashSet<super::InlineAsmReg>,
             >,
         ) {
+            #[allow(unused_imports)]
             use super::{InlineAsmReg, InlineAsmRegClass};
             $(
                 if $($filter(_arch, &mut _has_feature, true).is_ok() &&)? true {
-                    if let Some(set) = map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {
+                    if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {
                         set.insert(InlineAsmReg::$arch($arch_reg::$reg));
                     }
                     $(
-                        if let Some(set) = map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$extra_class)) {
+                        if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$extra_class)) {
                             set.insert(InlineAsmReg::$arch($arch_reg::$reg));
                         }
                     )*
@@ -146,11 +148,13 @@ macro_rules! types {
 
 mod aarch64;
 mod arm;
+mod nvptx;
 mod riscv;
 mod x86;
 
 pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
 pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
+pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
 pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
 pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
 
@@ -162,6 +166,7 @@ pub enum InlineAsmArch {
     AArch64,
     RiscV32,
     RiscV64,
+    Nvptx64,
 }
 
 impl FromStr for InlineAsmArch {
@@ -175,6 +180,7 @@ impl FromStr for InlineAsmArch {
             "aarch64" => Ok(Self::AArch64),
             "riscv32" => Ok(Self::RiscV32),
             "riscv64" => Ok(Self::RiscV64),
+            "nvptx64" => Ok(Self::Nvptx64),
             _ => Err(()),
         }
     }
@@ -196,6 +202,7 @@ pub enum InlineAsmReg {
     Arm(ArmInlineAsmReg),
     AArch64(AArch64InlineAsmReg),
     RiscV(RiscVInlineAsmReg),
+    Nvptx(NvptxInlineAsmReg),
 }
 
 impl InlineAsmReg {
@@ -236,6 +243,9 @@ impl InlineAsmReg {
             InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
                 Self::RiscV(RiscVInlineAsmReg::parse(arch, has_feature, &name)?)
             }
+            InlineAsmArch::Nvptx64 => {
+                Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, &name)?)
+            }
         })
     }
 
@@ -281,6 +291,7 @@ pub enum InlineAsmRegClass {
     Arm(ArmInlineAsmRegClass),
     AArch64(AArch64InlineAsmRegClass),
     RiscV(RiscVInlineAsmRegClass),
+    Nvptx(NvptxInlineAsmRegClass),
 }
 
 impl InlineAsmRegClass {
@@ -290,6 +301,7 @@ impl InlineAsmRegClass {
             Self::Arm(r) => r.name(),
             Self::AArch64(r) => r.name(),
             Self::RiscV(r) => r.name(),
+            Self::Nvptx(r) => r.name(),
         }
     }
 
@@ -302,6 +314,7 @@ impl InlineAsmRegClass {
             Self::Arm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Arm),
             Self::AArch64(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::AArch64),
             Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
+            Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
         }
     }
 
@@ -321,6 +334,7 @@ impl InlineAsmRegClass {
             Self::Arm(r) => r.suggest_modifier(arch, ty),
             Self::AArch64(r) => r.suggest_modifier(arch, ty),
             Self::RiscV(r) => r.suggest_modifier(arch, ty),
+            Self::Nvptx(r) => r.suggest_modifier(arch, ty),
         }
     }
 
@@ -336,6 +350,7 @@ impl InlineAsmRegClass {
             Self::Arm(r) => r.default_modifier(arch),
             Self::AArch64(r) => r.default_modifier(arch),
             Self::RiscV(r) => r.default_modifier(arch),
+            Self::Nvptx(r) => r.default_modifier(arch),
         }
     }
 
@@ -350,6 +365,7 @@ impl InlineAsmRegClass {
             Self::Arm(r) => r.supported_types(arch),
             Self::AArch64(r) => r.supported_types(arch),
             Self::RiscV(r) => r.supported_types(arch),
+            Self::Nvptx(r) => r.supported_types(arch),
         }
     }
 
@@ -367,6 +383,7 @@ impl InlineAsmRegClass {
                 InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
                     Self::RiscV(RiscVInlineAsmRegClass::parse(arch, name)?)
                 }
+                InlineAsmArch::Nvptx64 => Self::Nvptx(NvptxInlineAsmRegClass::parse(arch, name)?),
             })
         })
     }
@@ -379,6 +396,7 @@ impl InlineAsmRegClass {
             Self::Arm(r) => r.valid_modifiers(arch),
             Self::AArch64(r) => r.valid_modifiers(arch),
             Self::RiscV(r) => r.valid_modifiers(arch),
+            Self::Nvptx(r) => r.valid_modifiers(arch),
         }
     }
 }
@@ -518,5 +536,10 @@ pub fn allocatable_registers(
             riscv::fill_reg_map(arch, has_feature, &mut map);
             map
         }
+        InlineAsmArch::Nvptx64 => {
+            let mut map = nvptx::regclass_map();
+            nvptx::fill_reg_map(arch, has_feature, &mut map);
+            map
+        }
     }
 }
diff --git a/src/librustc_target/asm/nvptx.rs b/src/librustc_target/asm/nvptx.rs
@@ -0,0 +1,49 @@
+use super::{InlineAsmArch, InlineAsmType};
+use rustc_macros::HashStable_Generic;
+
+def_reg_class! {
+    Nvptx NvptxInlineAsmRegClass {
+        reg16,
+        reg32,
+        reg64,
+    }
+}
+
+impl NvptxInlineAsmRegClass {
+    pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char] {
+        &[]
+    }
+
+    pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
+        None
+    }
+
+    pub fn suggest_modifier(
+        self,
+        _arch: InlineAsmArch,
+        _ty: InlineAsmType,
+    ) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn supported_types(
+        self,
+        _arch: InlineAsmArch,
+    ) -> &'static [(InlineAsmType, Option<&'static str>)] {
+        match self {
+            Self::reg16 => types! { _: I8, I16; },
+            Self::reg32 => types! { _: I8, I16, I32, F32; },
+            Self::reg64 => types! { _: I8, I16, I32, F32, I64, F64; },
+        }
+    }
+}
+
+def_regs! {
+    // Registers in PTX are declared in the assembly.
+    // There are no predefined registers that one can use.
+    Nvptx NvptxInlineAsmReg NvptxInlineAsmRegClass {}
+}
diff --git a/src/test/assembly/asm/nvptx-types.rs b/src/test/assembly/asm/nvptx-types.rs

Original file line number	Diff line number	Diff line change
`@@ -254,6 +254,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {`
`254`	`254`	`]);`
`255`	`255`	`}`
`256`	`256`	`InlineAsmArch::RiscV32 \| InlineAsmArch::RiscV64 => {}`
	`257`	`+ InlineAsmArch::Nvptx64 => {}`
`257`	`258`	`}`
`258`	`259`	`}`
`259`	`260`	`if !options.contains(InlineAsmOptions::NOMEM) {`
`@@ -410,6 +411,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass) -> String {`
`410`	`411`	`\| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",`
`411`	`412`	`InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)`
`412`	`413`	`\| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",`
	`414`	`+ InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",`
	`415`	`+ InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",`
	`416`	`+ InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",`
`413`	`417`	`InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",`
`414`	`418`	`InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f",`
`415`	`419`	`InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",`
`@@ -452,6 +456,7 @@ fn modifier_to_llvm(`
`452`	`456`	`modifier`
`453`	`457`	`}`
`454`	`458`	`}`
	`459`	`+ InlineAsmRegClass::Nvptx(_) => None,`
`455`	`460`	`InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)`
`456`	`461`	`\| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,`
`457`	`462`	`InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)`
`@@ -502,6 +507,9 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll`
`502`	`507`	`\| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {`
`503`	`508`	`cx.type_vector(cx.type_i64(), 2)`
`504`	`509`	`}`
	`510`	`+ InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),`
	`511`	`+ InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),`
	`512`	`+ InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),`
`505`	`513`	`InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),`
`506`	`514`	`InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),`
`507`	`515`	`InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)`
Original file line number	Diff line number	Diff line change
`@@ -60,6 +60,7 @@ macro_rules! def_regs {`
`60`	`60`	`#error = [$($bad_reg:literal),+] => $error:literal,`
`61`	`61`	`)*`
`62`	`62`	`}) => {`
	`63`	`+ #[allow(unreachable_code)]`
`63`	`64`	`#[derive(Copy, Clone, RustcEncodable, RustcDecodable, Debug, Eq, PartialEq, Hash, HashStable_Generic)]`
`64`	`65`	`#[allow(non_camel_case_types)]`
`65`	`66`	`pub enum $arch_reg {`
`@@ -102,19 +103,20 @@ macro_rules! def_regs {`
`102`	`103`	`pub(super) fn fill_reg_map(`
`103`	`104`	`_arch: super::InlineAsmArch,`
`104`	`105`	`mut _has_feature: impl FnMut(&str) -> bool,`
`105`		`- map: &mut rustc_data_structures::fx::FxHashMap<`
	`106`	`+ _map: &mut rustc_data_structures::fx::FxHashMap<`
`106`	`107`	`super::InlineAsmRegClass,`
`107`	`108`	`rustc_data_structures::fx::FxHashSet<super::InlineAsmReg>,`
`108`	`109`	`>,`
`109`	`110`	`) {`
	`111`	`+ #[allow(unused_imports)]`
`110`	`112`	`use super::{InlineAsmReg, InlineAsmRegClass};`
`111`	`113`	`$(`
`112`	`114`	`if $($filter(_arch, &mut _has_feature, true).is_ok() &&)? true {`
`113`		`- if let Some(set) = map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {`
	`115`	`+ if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {`
`114`	`116`	`set.insert(InlineAsmReg::$arch($arch_reg::$reg));`
`115`	`117`	`}`
`116`	`118`	`$(`
`117`		`- if let Some(set) = map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$extra_class)) {`
	`119`	`+ if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$extra_class)) {`
`118`	`120`	`set.insert(InlineAsmReg::$arch($arch_reg::$reg));`
`119`	`121`	`}`
`120`	`122`	`)*`
`@@ -146,11 +148,13 @@ macro_rules! types {`
`146`	`148`
`147`	`149`	`mod aarch64;`
`148`	`150`	`mod arm;`
	`151`	`+mod nvptx;`
`149`	`152`	`mod riscv;`
`150`	`153`	`mod x86;`
`151`	`154`
`152`	`155`	`pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};`
`153`	`156`	`pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};`
	`157`	`+pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};`
`154`	`158`	`pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};`
`155`	`159`	`pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};`
`156`	`160`
`@@ -162,6 +166,7 @@ pub enum InlineAsmArch {`
`162`	`166`	`AArch64,`
`163`	`167`	`RiscV32,`
`164`	`168`	`RiscV64,`
	`169`	`+ Nvptx64,`
`165`	`170`	`}`
`166`	`171`
`167`	`172`	`impl FromStr for InlineAsmArch {`
`@@ -175,6 +180,7 @@ impl FromStr for InlineAsmArch {`
`175`	`180`	`"aarch64" => Ok(Self::AArch64),`
`176`	`181`	`"riscv32" => Ok(Self::RiscV32),`
`177`	`182`	`"riscv64" => Ok(Self::RiscV64),`
	`183`	`+ "nvptx64" => Ok(Self::Nvptx64),`
`178`	`184`	`_ => Err(()),`
`179`	`185`	`}`
`180`	`186`	`}`
`@@ -196,6 +202,7 @@ pub enum InlineAsmReg {`
`196`	`202`	`Arm(ArmInlineAsmReg),`
`197`	`203`	`AArch64(AArch64InlineAsmReg),`
`198`	`204`	`RiscV(RiscVInlineAsmReg),`
	`205`	`+ Nvptx(NvptxInlineAsmReg),`
`199`	`206`	`}`
`200`	`207`
`201`	`208`	`impl InlineAsmReg {`
`@@ -236,6 +243,9 @@ impl InlineAsmReg {`
`236`	`243`	`InlineAsmArch::RiscV32 \| InlineAsmArch::RiscV64 => {`
`237`	`244`	`Self::RiscV(RiscVInlineAsmReg::parse(arch, has_feature, &name)?)`
`238`	`245`	`}`
	`246`	`+ InlineAsmArch::Nvptx64 => {`
	`247`	`+ Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, &name)?)`
	`248`	`+ }`
`239`	`249`	`})`
`240`	`250`	`}`
`241`	`251`
`@@ -281,6 +291,7 @@ pub enum InlineAsmRegClass {`
`281`	`291`	`Arm(ArmInlineAsmRegClass),`
`282`	`292`	`AArch64(AArch64InlineAsmRegClass),`
`283`	`293`	`RiscV(RiscVInlineAsmRegClass),`
	`294`	`+ Nvptx(NvptxInlineAsmRegClass),`
`284`	`295`	`}`
`285`	`296`
`286`	`297`	`impl InlineAsmRegClass {`
`@@ -290,6 +301,7 @@ impl InlineAsmRegClass {`
`290`	`301`	`Self::Arm(r) => r.name(),`
`291`	`302`	`Self::AArch64(r) => r.name(),`
`292`	`303`	`Self::RiscV(r) => r.name(),`
	`304`	`+ Self::Nvptx(r) => r.name(),`
`293`	`305`	`}`
`294`	`306`	`}`
`295`	`307`
`@@ -302,6 +314,7 @@ impl InlineAsmRegClass {`
`302`	`314`	`Self::Arm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Arm),`
`303`	`315`	`Self::AArch64(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::AArch64),`
`304`	`316`	`Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),`
	`317`	`+ Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),`
`305`	`318`	`}`
`306`	`319`	`}`
`307`	`320`
`@@ -321,6 +334,7 @@ impl InlineAsmRegClass {`
`321`	`334`	`Self::Arm(r) => r.suggest_modifier(arch, ty),`
`322`	`335`	`Self::AArch64(r) => r.suggest_modifier(arch, ty),`
`323`	`336`	`Self::RiscV(r) => r.suggest_modifier(arch, ty),`
	`337`	`+ Self::Nvptx(r) => r.suggest_modifier(arch, ty),`
`324`	`338`	`}`
`325`	`339`	`}`
`326`	`340`
`@@ -336,6 +350,7 @@ impl InlineAsmRegClass {`
`336`	`350`	`Self::Arm(r) => r.default_modifier(arch),`
`337`	`351`	`Self::AArch64(r) => r.default_modifier(arch),`
`338`	`352`	`Self::RiscV(r) => r.default_modifier(arch),`
	`353`	`+ Self::Nvptx(r) => r.default_modifier(arch),`
`339`	`354`	`}`
`340`	`355`	`}`
`341`	`356`
`@@ -350,6 +365,7 @@ impl InlineAsmRegClass {`
`350`	`365`	`Self::Arm(r) => r.supported_types(arch),`
`351`	`366`	`Self::AArch64(r) => r.supported_types(arch),`
`352`	`367`	`Self::RiscV(r) => r.supported_types(arch),`
	`368`	`+ Self::Nvptx(r) => r.supported_types(arch),`
`353`	`369`	`}`
`354`	`370`	`}`
`355`	`371`
`@@ -367,6 +383,7 @@ impl InlineAsmRegClass {`
`367`	`383`	`InlineAsmArch::RiscV32 \| InlineAsmArch::RiscV64 => {`
`368`	`384`	`Self::RiscV(RiscVInlineAsmRegClass::parse(arch, name)?)`
`369`	`385`	`}`
	`386`	`+ InlineAsmArch::Nvptx64 => Self::Nvptx(NvptxInlineAsmRegClass::parse(arch, name)?),`
`370`	`387`	`})`
`371`	`388`	`})`
`372`	`389`	`}`
`@@ -379,6 +396,7 @@ impl InlineAsmRegClass {`
`379`	`396`	`Self::Arm(r) => r.valid_modifiers(arch),`
`380`	`397`	`Self::AArch64(r) => r.valid_modifiers(arch),`
`381`	`398`	`Self::RiscV(r) => r.valid_modifiers(arch),`
	`399`	`+ Self::Nvptx(r) => r.valid_modifiers(arch),`
`382`	`400`	`}`
`383`	`401`	`}`
`384`	`402`	`}`
`@@ -518,5 +536,10 @@ pub fn allocatable_registers(`
`518`	`536`	`riscv::fill_reg_map(arch, has_feature, &mut map);`
`519`	`537`	`map`
`520`	`538`	`}`
	`539`	`+ InlineAsmArch::Nvptx64 => {`
	`540`	`+ let mut map = nvptx::regclass_map();`
	`541`	`+ nvptx::fill_reg_map(arch, has_feature, &mut map);`
	`542`	`+ map`
	`543`	`+ }`
`521`	`544`	`}`
`522`	`545`	`}`