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🚸 Tronxy V10 w/ TFT_TRONXY_X5SA + MKS_ROBIN_TFT43 (MarlinFirmware#26747)
1 parent 755b661 commit 9364cbb

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9 files changed

+437
-366
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9 files changed

+437
-366
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‎Marlin/src/HAL/STM32/tft/tft_fsmc.cpp

+72-66
Original file line numberDiff line numberDiff line change
@@ -37,50 +37,61 @@ LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD;
3737

3838
void TFT_FSMC::init() {
3939
uint32_t controllerAddress;
40-
FSMC_NORSRAM_TimingTypeDef timing, extTiming;
40+
FMC_OR_FSMC(NORSRAM_TimingTypeDef) timing, extTiming;
4141

4242
uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS);
4343

4444
// Perform the SRAM1 memory initialization sequence
45-
SRAMx.Instance = FSMC_NORSRAM_DEVICE;
46-
SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
45+
SRAMx.Instance = FMC_OR_FSMC(NORSRAM_DEVICE);
46+
SRAMx.Extended = FMC_OR_FSMC(NORSRAM_EXTENDED_DEVICE);
47+
4748
// SRAMx.Init
4849
SRAMx.Init.NSBank = nsBank;
49-
SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
50-
SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
51-
SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16);
52-
SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
53-
SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
54-
SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
55-
SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
56-
SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
57-
SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
58-
SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE;
59-
SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
60-
SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
61-
#ifdef STM32F4xx
62-
SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE;
50+
SRAMx.Init.DataAddressMux = FMC_OR_FSMC(DATA_ADDRESS_MUX_DISABLE);
51+
SRAMx.Init.MemoryType = FMC_OR_FSMC(MEMORY_TYPE_SRAM);
52+
#ifdef STM32F446xx
53+
SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16);
54+
#else
55+
SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16);
56+
#endif
57+
SRAMx.Init.BurstAccessMode = FMC_OR_FSMC(BURST_ACCESS_MODE_DISABLE);
58+
SRAMx.Init.WaitSignalPolarity = FMC_OR_FSMC(WAIT_SIGNAL_POLARITY_LOW);
59+
SRAMx.Init.WrapMode = FMC_OR_FSMC(WRAP_MODE_DISABLE);
60+
SRAMx.Init.WaitSignalActive = FMC_OR_FSMC(WAIT_TIMING_BEFORE_WS);
61+
SRAMx.Init.WriteOperation = FMC_OR_FSMC(WRITE_OPERATION_ENABLE);
62+
SRAMx.Init.WaitSignal = FMC_OR_FSMC(WAIT_SIGNAL_DISABLE);
63+
SRAMx.Init.ExtendedMode = FMC_OR_FSMC(EXTENDED_MODE_ENABLE);
64+
SRAMx.Init.AsynchronousWait = FMC_OR_FSMC(ASYNCHRONOUS_WAIT_DISABLE);
65+
SRAMx.Init.WriteBurst = FMC_OR_FSMC(WRITE_BURST_DISABLE);
66+
#if defined(STM32F446xx) || defined(STM32F4xx)
67+
SRAMx.Init.PageSize = FMC_OR_FSMC(PAGE_SIZE_NONE);
6368
#endif
69+
6470
// Read Timing - relatively slow to ensure ID information is correctly read from TFT controller
65-
// Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss
66-
timing.AddressSetupTime = 15;
67-
timing.AddressHoldTime = 15;
68-
timing.DataSetupTime = 24;
69-
timing.BusTurnAroundDuration = 0;
70-
timing.CLKDivision = 16;
71-
timing.DataLatency = 17;
72-
timing.AccessMode = FSMC_ACCESS_MODE_A;
71+
// Can be decreased from 15-15-24 to 4-4-8 with risk of stability loss
72+
timing.AddressSetupTime = 15;
73+
timing.AddressHoldTime = 15;
74+
timing.DataSetupTime = 24;
75+
timing.BusTurnAroundDuration = 0;
76+
timing.CLKDivision = 16;
77+
timing.DataLatency = 17;
78+
timing.AccessMode = FMC_OR_FSMC(ACCESS_MODE_A);
79+
7380
// Write Timing
7481
// Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss
75-
extTiming.AddressSetupTime = 8;
76-
extTiming.AddressHoldTime = 15;
77-
extTiming.DataSetupTime = 8;
78-
extTiming.BusTurnAroundDuration = 0;
79-
extTiming.CLKDivision = 16;
80-
extTiming.DataLatency = 17;
81-
extTiming.AccessMode = FSMC_ACCESS_MODE_A;
82-
83-
__HAL_RCC_FSMC_CLK_ENABLE();
82+
extTiming.AddressSetupTime = 8;
83+
extTiming.AddressHoldTime = 15;
84+
extTiming.DataSetupTime = 8;
85+
extTiming.BusTurnAroundDuration = 0;
86+
extTiming.CLKDivision = 16;
87+
extTiming.DataLatency = 17;
88+
extTiming.AccessMode = FMC_OR_FSMC(ACCESS_MODE_A);
89+
90+
#ifdef STM32F446xx
91+
__HAL_RCC_FMC_CLK_ENABLE();
92+
#else
93+
__HAL_RCC_FSMC_CLK_ENABLE();
94+
#endif
8495

8596
for (uint16_t i = 0; pinMap_FSMC[i].pin != NC; i++)
8697
pinmap_pinout(pinMap_FSMC[i].pin, pinMap_FSMC);
@@ -90,59 +101,54 @@ void TFT_FSMC::init() {
90101
controllerAddress = FSMC_BANK1_1;
91102
#ifdef PF0
92103
switch (nsBank) {
93-
case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break;
94-
case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break;
95-
case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break;
104+
case FMC_OR_FSMC(NORSRAM_BANK2): controllerAddress = FSMC_BANK1_2; break;
105+
case FMC_OR_FSMC(NORSRAM_BANK3): controllerAddress = FSMC_BANK1_3; break;
106+
case FMC_OR_FSMC(NORSRAM_BANK4): controllerAddress = FSMC_BANK1_4; break;
96107
}
97108
#endif
98109

99110
controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS);
100111

101112
HAL_SRAM_Init(&SRAMx, &timing, &extTiming);
102113

114+
__HAL_RCC_DMA2_CLK_ENABLE();
115+
103116
#ifdef STM32F1xx
104-
__HAL_RCC_DMA1_CLK_ENABLE();
105-
DMAtx.Instance = DMA1_Channel1;
117+
DMAtx.Instance = DMA2_Channel1;
106118
#elif defined(STM32F4xx)
107-
__HAL_RCC_DMA2_CLK_ENABLE();
108-
DMAtx.Instance = DMA2_Stream0;
109-
DMAtx.Init.Channel = DMA_CHANNEL_0;
110-
DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
111-
DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
112-
DMAtx.Init.MemBurst = DMA_MBURST_SINGLE;
113-
DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE;
119+
DMAtx.Instance = DMA2_Stream0;
120+
DMAtx.Init.Channel = DMA_CHANNEL_0;
121+
DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
122+
DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
123+
DMAtx.Init.MemBurst = DMA_MBURST_SINGLE;
124+
DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE;
114125
#endif
115126

116-
DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY;
117-
DMAtx.Init.MemInc = DMA_MINC_DISABLE;
118-
DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
119-
DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
120-
DMAtx.Init.Mode = DMA_NORMAL;
121-
DMAtx.Init.Priority = DMA_PRIORITY_HIGH;
127+
DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY;
128+
DMAtx.Init.MemInc = DMA_MINC_DISABLE;
129+
DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
130+
DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
131+
DMAtx.Init.Mode = DMA_NORMAL;
132+
DMAtx.Init.Priority = DMA_PRIORITY_HIGH;
122133

123134
LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress;
124135
}
125136

126137
uint32_t TFT_FSMC::getID() {
127-
uint32_t id;
128138
writeReg(0);
129-
id = LCD->RAM;
130-
131-
if (id == 0)
132-
id = readID(LCD_READ_ID);
133-
if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF)
134-
id = readID(LCD_READ_ID4);
139+
uint32_t id = LCD->RAM;
140+
if (id == 0) id = readID(LCD_READ_ID);
141+
if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) id = readID(LCD_READ_ID4);
135142
return id;
136143
}
137144

138-
uint32_t TFT_FSMC::readID(const tft_data_t inReg) {
139-
uint32_t id;
145+
uint32_t TFT_FSMC::readID(tft_data_t inReg) {
140146
writeReg(inReg);
141-
id = LCD->RAM; // dummy read
147+
uint32_t id = LCD->RAM; // dummy read
142148
id = inReg << 24;
143149
id |= (LCD->RAM & 0x00FF) << 16;
144150
id |= (LCD->RAM & 0x00FF) << 8;
145-
id |= LCD->RAM & 0x00FF;
151+
id |= (LCD->RAM & 0x00FF);
146152
return id;
147153
}
148154

@@ -155,7 +161,9 @@ bool TFT_FSMC::isBusy() {
155161
#define __IS_DMA_CONFIGURED(__HANDLE__) ((__HANDLE__)->Instance->PAR != 0)
156162
#endif
157163

158-
if (!__IS_DMA_CONFIGURED(&DMAtx)) return false;
164+
#ifdef __IS_DMA_CONFIGURED
165+
if (!__IS_DMA_CONFIGURED(&DMAtx)) return false;
166+
#endif
159167

160168
// Check if DMA transfer error or transfer complete flags are set
161169
if ((__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TE_FLAG_INDEX(&DMAtx)) == 0) && (__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TC_FLAG_INDEX(&DMAtx)) == 0)) return true;
@@ -174,8 +182,6 @@ void TFT_FSMC::transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t cou
174182
DMAtx.Init.PeriphInc = memoryIncrease;
175183
HAL_DMA_Init(&DMAtx);
176184
HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count);
177-
178-
TERN_(TFT_SHARED_IO, while (isBusy()));
179185
}
180186

181187
void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) {

‎Marlin/src/HAL/STM32/tft/tft_fsmc.h

+35-29
Original file line numberDiff line numberDiff line change
@@ -28,11 +28,7 @@
2828
#elif defined(STM32F4xx)
2929
#include "stm32f4xx_hal.h"
3030
#else
31-
#error "FSMC TFT is currently only supported on STM32F1 and STM32F4 hardware."
32-
#endif
33-
34-
#ifndef HAL_SRAM_MODULE_ENABLED
35-
#error "SRAM module disabled for the STM32 framework (HAL_SRAM_MODULE_ENABLED)! Please consult the development team."
31+
#error "FSMC/FMC TFT is currently only supported on STM32F1 and STM32F4 hardware."
3632
#endif
3733

3834
#ifndef LCD_READ_ID
@@ -55,14 +51,20 @@ typedef struct {
5551
__IO tft_data_t RAM;
5652
} LCD_CONTROLLER_TypeDef;
5753

54+
#ifdef STM32F446xx
55+
#define FMC_OR_FSMC(N) _CAT(FMC_, N)
56+
#else
57+
#define FMC_OR_FSMC(N) _CAT(FSMC_, N)
58+
#endif
59+
5860
class TFT_FSMC {
5961
private:
6062
static SRAM_HandleTypeDef SRAMx;
6163
static DMA_HandleTypeDef DMAtx;
6264

6365
static LCD_CONTROLLER_TypeDef *LCD;
6466

65-
static uint32_t readID(const tft_data_t reg);
67+
static uint32_t readID(tft_data_t inReg);
6668
static void transmit(tft_data_t data) { LCD->RAM = data; __DSB(); }
6769
static void transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count);
6870
static void transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count);
@@ -94,7 +96,11 @@ class TFT_FSMC {
9496
#ifdef STM32F1xx
9597
#define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE)
9698
#elif defined(STM32F4xx)
97-
#define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC)
99+
#ifdef STM32F446xx
100+
#define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)
101+
#else
102+
#define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC)
103+
#endif
98104
#define FSMC_BANK1_1 0x60000000U
99105
#define FSMC_BANK1_2 0x64000000U
100106
#define FSMC_BANK1_3 0x68000000U
@@ -104,35 +110,35 @@ class TFT_FSMC {
104110
#endif
105111

106112
const PinMap pinMap_FSMC[] = {
107-
{PD_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00
108-
{PD_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01
109-
{PD_0, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02
110-
{PD_1, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03
111-
{PE_7, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04
112-
{PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05
113-
{PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06
114-
{PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07
113+
{PD_14, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D00
114+
{PD_15, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D01
115+
{PD_0, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D02
116+
{PD_1, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D03
117+
{PE_7, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D04
118+
{PE_8, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D05
119+
{PE_9, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D06
120+
{PE_10, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D07
115121
#if DISABLED(TFT_INTERFACE_FSMC_8BIT)
116-
{PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08
117-
{PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09
118-
{PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10
119-
{PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11
120-
{PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12
121-
{PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13
122-
{PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14
123-
{PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15
122+
{PE_11, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D08
123+
{PE_12, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D09
124+
{PE_13, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D10
125+
{PE_14, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D11
126+
{PE_15, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D12
127+
{PD_8, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D13
128+
{PD_9, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D14
129+
{PD_10, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D15
124130
#endif
125-
{PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE
126-
{PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE
131+
{PD_4, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_NOE
132+
{PD_5, FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_NWE
127133
{NC, NP, 0}
128134
};
129135

130136
const PinMap pinMap_FSMC_CS[] = {
131-
{PD_7, (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1
137+
{PD_7, (void *)FMC_OR_FSMC(NORSRAM_BANK1), FSMC_PIN_DATA}, // FSMC_NE1
132138
#ifdef PF0
133-
{PG_9, (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2
134-
{PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3
135-
{PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4
139+
{PG_9, (void *)FMC_OR_FSMC(NORSRAM_BANK2), FSMC_PIN_DATA}, // FSMC_NE2
140+
{PG_10, (void *)FMC_OR_FSMC(NORSRAM_BANK3), FSMC_PIN_DATA}, // FSMC_NE3
141+
{PG_12, (void *)FMC_OR_FSMC(NORSRAM_BANK4), FSMC_PIN_DATA}, // FSMC_NE4
136142
#endif
137143
{NC, NP, 0}
138144
};

‎Marlin/src/core/boards.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -459,7 +459,7 @@
459459
#define BOARD_OPULO_LUMEN_REV4 5242 // Opulo Lumen PnP Controller REV4 (STM32F407VE / STM32F407VG)
460460
#define BOARD_FYSETC_SPIDER_KING407 5243 // FYSETC Spider King407 (STM32F407ZG)
461461
#define BOARD_MKS_SKIPR_V1 5244 // MKS SKIPR v1.0 all-in-one board (STM32F407VE)
462-
#define BOARD_TRONXY_V10 5245 // TRONXY V10 (STM32F446ZE)
462+
#define BOARD_TRONXY_CXY_446_V10 5245 // TRONXY CXY-446-V10-220413/CXY-V6-191121 (STM32F446ZE)
463463
#define BOARD_CREALITY_F401RE 5246 // Creality CR4NS200141C13 (STM32F401RE) as found in the Ender-5 S1
464464
#define BOARD_BLACKPILL_CUSTOM 5247 // Custom board based on STM32F401CDU6.
465465
#define BOARD_I3DBEEZ9_V1 5248 // I3DBEEZ9 V1 (STM32F407ZG)

‎Marlin/src/pins/pins.h

+6-2
Original file line numberDiff line numberDiff line change
@@ -806,8 +806,8 @@
806806
#include "stm32f4/pins_FYSETC_SPIDER_KING407.h" // STM32F4 env:FYSETC_SPIDER_KING407
807807
#elif MB(MKS_SKIPR_V1)
808808
#include "stm32f4/pins_MKS_SKIPR_V1_0.h" // STM32F4 env:mks_skipr_v1 env:mks_skipr_v1_nobootloader
809-
#elif MB(TRONXY_V10)
810-
#include "stm32f4/pins_TRONXY_V10.h" // STM32F4 env:STM32F446_tronxy
809+
#elif MB(TRONXY_CXY_446_V10)
810+
#include "stm32f4/pins_TRONXY_CXY_446_V10.h" // STM32F4 env:TRONXY_CXY_446_V10 env:TRONXY_CXY_446_V10_usb_flash_drive
811811
#elif MB(CREALITY_F401RE)
812812
#include "stm32f4/pins_CREALITY_F401.h" // STM32F4 env:STM32F401RE_creality
813813
#elif MB(BLACKPILL_CUSTOM)
@@ -956,6 +956,7 @@
956956
#define BOARD_LINUX_RAMPS 99926
957957
#define BOARD_BTT_MANTA_M4P_V1_0 99927
958958
#define BOARD_VAKE403D 99928
959+
#define BOARD_TRONXY_V10 99929
959960

960961
#if MB(MKS_13)
961962
#error "BOARD_MKS_13 is now BOARD_MKS_GEN_13. Please update your configuration."
@@ -1015,6 +1016,8 @@
10151016
#error "BOARD_LINUX_RAMPS is now BOARD_SIMULATED. Please update your configuration."
10161017
#elif MB(BTT_MANTA_M4P_V1_0)
10171018
#error "BOARD_BTT_MANTA_M4P_V1_0 is now BOARD_BTT_MANTA_M4P_V2_1. Please update your configuration."
1019+
#elif MB(TRONXY_V10)
1020+
#error "BOARD_TRONXY_V10 is now BOARD_TRONXY_CXY_446_V10. Please update your configuration."
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#elif MB(VAKE403D)
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#error "BOARD_VAKE403D is no longer supported in Marlin."
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#elif defined(MOTHERBOARD)
@@ -1053,6 +1056,7 @@
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#undef BOARD_LINUX_RAMPS
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#undef BOARD_BTT_MANTA_M4P_V1_0
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#undef BOARD_VAKE403D
1059+
#undef BOARD_TRONXY_V10
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#endif
10581062

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