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ppc476: Enable a linker work around for IBM errata torvalds#46
This patch adds an option to enable a work around for an icache bug on 476 that can cause execution of stale instructions when falling through pages (IBM errata torvalds#46). It requires a recent version of binutils which supports the --ppc476-workaround option. The work around enables the appropriate linker options and ensures that all module output sections are aligned to 4K page boundaries. The work around is only required when building modules. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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arch/powerpc/Makefile

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@@ -159,6 +159,11 @@ CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)
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KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
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ifeq ($(CONFIG_476FPE_ERR46),y)
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KBUILD_LDFLAGS_MODULE += --ppc476-workaround \
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-T $(srctree)/arch/powerpc/platforms/44x/ppc476_modules.lds
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endif
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# No AltiVec or VSX instructions when building kernel
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KBUILD_CFLAGS += $(call cc-option,-mno-altivec)
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KBUILD_CFLAGS += $(call cc-option,-mno-vsx)

arch/powerpc/platforms/44x/Kconfig

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@@ -351,6 +351,20 @@ config APM821xx
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select IBM_EMAC_EMAC4
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select IBM_EMAC_TAH
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config 476FPE_ERR46
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depends on 476FPE
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bool "Enable linker work around for PPC476FPE errata #46"
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help
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This option enables a work around for an icache bug on 476
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that can cause execution of stale instructions when falling
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through pages (IBM errata #46). It requires a recent version
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of binutils which supports the --ppc476-workaround option.
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The work around enables the appropriate linker options and
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ensures that all module output sections are aligned to 4K
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page boundaries. The work around is only required when
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building modules.
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# 44x errata/workaround config symbols, selected by the CPU models above
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config IBM440EP_ERR42
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bool
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@@ -0,0 +1,15 @@
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SECTIONS
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{
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.text : ALIGN(4096)
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{
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*(.text .text.* .fixup)
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}
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.init.text : ALIGN(4096)
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{
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*(.init.text .init.text.*)
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}
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.exit.text : ALIGN(4096)
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{
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*(.exit.text .exit.text.*)
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}
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}

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