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KyleGospoKyleGospo
committedMar 19, 2024
feat(gamescope): Add HDR patch for Kernel 6.8
·
v3.7.041.20241029
1 parent a2e9928 commit f8ad9ab

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‎spec_files/gamescope/amd_hdr.patch

+349
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,349 @@
1+
diff --git a/src/drm.cpp b/src/drm.cpp
2+
index c975bfd..686c9b0 100644
3+
--- a/src/drm.cpp
4+
+++ b/src/drm.cpp
5+
@@ -1044,15 +1044,15 @@ static bool refresh_state( drm_t *drm )
6+
crtc->has_vrr_enabled = crtc->props.contains( "VRR_ENABLED" );
7+
if (!crtc->has_vrr_enabled)
8+
drm_log.infof("CRTC %" PRIu32 " has no VRR_ENABLED support", crtc->id);
9+
- crtc->has_valve1_regamma_tf = crtc->props.contains( "VALVE1_CRTC_REGAMMA_TF" );
10+
- if (!crtc->has_valve1_regamma_tf)
11+
- drm_log.infof("CRTC %" PRIu32 " has no VALVE1_CRTC_REGAMMA_TF support", crtc->id);
12+
+ crtc->has_amd_regamma_tf = crtc->props.contains( "AMD_CRTC_REGAMMA_TF" );
13+
+ if (!crtc->has_amd_regamma_tf)
14+
+ drm_log.infof("CRTC %" PRIu32 " has no AMD_CRTC_REGAMMA_TF support", crtc->id);
15+
16+
crtc->current.active = crtc->initial_prop_values["ACTIVE"];
17+
if (crtc->has_vrr_enabled)
18+
drm->current.vrr_enabled = crtc->initial_prop_values["VRR_ENABLED"];
19+
- if (crtc->has_valve1_regamma_tf)
20+
- drm->current.output_tf = (drm_valve1_transfer_function) crtc->initial_prop_values["VALVE1_CRTC_REGAMMA_TF"];
21+
+ if (crtc->has_amd_regamma_tf)
22+
+ drm->current.output_tf = (amdgpu_transfer_function) crtc->initial_prop_values["AMD_CRTC_REGAMMA_TF"];
23+
}
24+
25+
for (size_t i = 0; i < drm->planes.size(); i++) {
26+
@@ -1060,7 +1060,7 @@ static bool refresh_state( drm_t *drm )
27+
if (!get_object_properties(drm, plane->id, DRM_MODE_OBJECT_PLANE, plane->props, plane->initial_prop_values)) {
28+
return false;
29+
}
30+
- plane->has_color_mgmt = plane->props.contains( "VALVE1_PLANE_BLEND_TF" );
31+
+ plane->has_color_mgmt = plane->props.contains( "AMD_PLANE_BLEND_TF" );
32+
}
33+
34+
return true;
35+
@@ -1597,8 +1597,8 @@ void finish_drm(struct drm_t *drm)
36+
add_crtc_property(req, &drm->crtcs[i], "CTM", 0);
37+
if ( drm->crtcs[i].has_vrr_enabled )
38+
add_crtc_property(req, &drm->crtcs[i], "VRR_ENABLED", 0);
39+
- if ( drm->crtcs[i].has_valve1_regamma_tf )
40+
- add_crtc_property(req, &drm->crtcs[i], "VALVE1_CRTC_REGAMMA_TF", 0);
41+
+ if ( drm->crtcs[i].has_amd_regamma_tf )
42+
+ add_crtc_property(req, &drm->crtcs[i], "AMD_CRTC_REGAMMA_TF", 0);
43+
add_crtc_property(req, &drm->crtcs[i], "ACTIVE", 0);
44+
}
45+
for ( size_t i = 0; i < drm->planes.size(); i++ ) {
46+
@@ -1617,22 +1617,22 @@ void finish_drm(struct drm_t *drm)
47+
add_plane_property(req, plane, "rotation", DRM_MODE_ROTATE_0);
48+
if (plane->props.count("alpha") > 0)
49+
add_plane_property(req, plane, "alpha", 0xFFFF);
50+
- if (plane->props.count("VALVE1_PLANE_DEGAMMA_TF") > 0)
51+
- add_plane_property(req, plane, "VALVE1_PLANE_DEGAMMA_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
52+
- if (plane->props.count("VALVE1_PLANE_HDR_MULT") > 0)
53+
- add_plane_property(req, plane, "VALVE1_PLANE_HDR_MULT", 0x100000000ULL);
54+
- if (plane->props.count("VALVE1_PLANE_SHAPER_TF") > 0)
55+
- add_plane_property(req, plane, "VALVE1_PLANE_SHAPER_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
56+
- if (plane->props.count("VALVE1_PLANE_SHAPER_LUT") > 0)
57+
- add_plane_property(req, plane, "VALVE1_PLANE_SHAPER_LUT", 0 );
58+
- if (plane->props.count("VALVE1_PLANE_LUT3D") > 0)
59+
- add_plane_property(req, plane, "VALVE1_PLANE_LUT3D", 0 );
60+
- if (plane->props.count("VALVE1_PLANE_BLEND_TF") > 0)
61+
- add_plane_property(req, plane, "VALVE1_PLANE_BLEND_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
62+
- if (plane->props.count("VALVE1_PLANE_BLEND_LUT") > 0)
63+
- add_plane_property(req, plane, "VALVE1_PLANE_BLEND_LUT", 0 );
64+
- if (plane->props.count("VALVE1_PLANE_CTM") > 0)
65+
- add_plane_property(req, plane, "VALVE1_PLANE_CTM", 0 );
66+
+ if (plane->props.count("AMD_PLANE_DEGAMMA_TF") > 0)
67+
+ add_plane_property(req, plane, "AMD_PLANE_DEGAMMA_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
68+
+ if (plane->props.count("AMD_PLANE_HDR_MULT") > 0)
69+
+ add_plane_property(req, plane, "AMD_PLANE_HDR_MULT", 0x100000000ULL);
70+
+ if (plane->props.count("AMD_PLANE_SHAPER_TF") > 0)
71+
+ add_plane_property(req, plane, "AMD_PLANE_SHAPER_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
72+
+ if (plane->props.count("AMD_PLANE_SHAPER_LUT") > 0)
73+
+ add_plane_property(req, plane, "AMD_PLANE_SHAPER_LUT", 0 );
74+
+ if (plane->props.count("AMD_PLANE_LUT3D") > 0)
75+
+ add_plane_property(req, plane, "AMD_PLANE_LUT3D", 0 );
76+
+ if (plane->props.count("AMD_PLANE_BLEND_TF") > 0)
77+
+ add_plane_property(req, plane, "AMD_PLANE_BLEND_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
78+
+ if (plane->props.count("AMD_PLANE_BLEND_LUT") > 0)
79+
+ add_plane_property(req, plane, "AMD_PLANE_BLEND_LUT", 0 );
80+
+ if (plane->props.count("AMD_PLANE_CTM") > 0)
81+
+ add_plane_property(req, plane, "AMD_PLANE_CTM", 0 );
82+
}
83+
// We can't do a non-blocking commit here or else risk EBUSY in case the
84+
// previous page-flip is still in flight.
85+
@@ -2222,37 +2222,37 @@ struct LiftoffStateCacheEntryKasher
86+
87+
std::unordered_set<LiftoffStateCacheEntry, LiftoffStateCacheEntryKasher> g_LiftoffStateCache;
88+
89+
-static inline drm_valve1_transfer_function colorspace_to_plane_degamma_tf(GamescopeAppTextureColorspace colorspace)
90+
+static inline amdgpu_transfer_function colorspace_to_plane_degamma_tf(GamescopeAppTextureColorspace colorspace)
91+
{
92+
switch ( colorspace )
93+
{
94+
default: // Linear in this sense is SRGB. Linear = sRGB image view doing automatic sRGB -> Linear which doesn't happen on DRM side.
95+
case GAMESCOPE_APP_TEXTURE_COLORSPACE_SRGB:
96+
- return DRM_VALVE1_TRANSFER_FUNCTION_SRGB;
97+
+ return AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF;
98+
case GAMESCOPE_APP_TEXTURE_COLORSPACE_PASSTHRU:
99+
case GAMESCOPE_APP_TEXTURE_COLORSPACE_SCRGB:
100+
// Use LINEAR TF for scRGB float format as 80 nit = 1.0 in scRGB, which matches
101+
// what PQ TF decodes to/encodes from.
102+
// AMD internal format is FP16, and generally expected for 1.0 -> 80 nit.
103+
// which just so happens to match scRGB.
104+
- return DRM_VALVE1_TRANSFER_FUNCTION_LINEAR;
105+
+ return AMDGPU_TRANSFER_FUNCTION_IDENTITY;
106+
case GAMESCOPE_APP_TEXTURE_COLORSPACE_HDR10_PQ:
107+
- return DRM_VALVE1_TRANSFER_FUNCTION_PQ;
108+
+ return AMDGPU_TRANSFER_FUNCTION_PQ_EOTF;
109+
}
110+
}
111+
112+
-static inline drm_valve1_transfer_function colorspace_to_plane_shaper_tf(GamescopeAppTextureColorspace colorspace)
113+
+static inline amdgpu_transfer_function colorspace_to_plane_shaper_tf(GamescopeAppTextureColorspace colorspace)
114+
{
115+
switch ( colorspace )
116+
{
117+
default:
118+
case GAMESCOPE_APP_TEXTURE_COLORSPACE_SRGB:
119+
- return DRM_VALVE1_TRANSFER_FUNCTION_SRGB;
120+
+ return AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF;
121+
case GAMESCOPE_APP_TEXTURE_COLORSPACE_SCRGB: // scRGB Linear -> PQ for shaper + 3D LUT
122+
case GAMESCOPE_APP_TEXTURE_COLORSPACE_HDR10_PQ:
123+
- return DRM_VALVE1_TRANSFER_FUNCTION_PQ;
124+
+ return AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF;
125+
case GAMESCOPE_APP_TEXTURE_COLORSPACE_PASSTHRU:
126+
- return DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
127+
+ return AMDGPU_TRANSFER_FUNCTION_DEFAULT;
128+
}
129+
}
130+
131+
@@ -2403,8 +2403,8 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
132+
133+
if ( drm_supports_color_mgmt( drm ) )
134+
{
135+
- drm_valve1_transfer_function degamma_tf = colorspace_to_plane_degamma_tf( entry.layerState[i].colorspace );
136+
- drm_valve1_transfer_function shaper_tf = colorspace_to_plane_shaper_tf( entry.layerState[i].colorspace );
137+
+ amdgpu_transfer_function degamma_tf = colorspace_to_plane_degamma_tf( entry.layerState[i].colorspace );
138+
+ amdgpu_transfer_function shaper_tf = colorspace_to_plane_shaper_tf( entry.layerState[i].colorspace );
139+
140+
if ( entry.layerState[i].ycbcr )
141+
{
142+
@@ -2416,27 +2416,27 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
143+
//
144+
// Doing LINEAR/DEFAULT here introduces banding so... this is the best way.
145+
// (sRGB DEGAMMA does NOT work on YUV planes!)
146+
- degamma_tf = DRM_VALVE1_TRANSFER_FUNCTION_BT709;
147+
- shaper_tf = DRM_VALVE1_TRANSFER_FUNCTION_BT709;
148+
+ degamma_tf = AMDGPU_TRANSFER_FUNCTION_BT709_OETF;
149+
+ shaper_tf = AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF;
150+
}
151+
152+
if (!g_bDisableDegamma)
153+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", degamma_tf );
154+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", degamma_tf );
155+
else
156+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", 0 );
157+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", 0 );
158+
159+
if ( !g_bDisableShaperAnd3DLUT )
160+
{
161+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", drm->pending.shaperlut_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
162+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", shaper_tf );
163+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", drm->pending.lut3d_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
164+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", drm->pending.shaperlut_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
165+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", shaper_tf );
166+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", drm->pending.lut3d_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
167+
// Josh: See shaders/colorimetry.h colorspace_blend_tf if you have questions as to why we start doing sRGB for BLEND_TF despite potentially working in Gamma 2.2 space prior.
168+
}
169+
else
170+
{
171+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", 0 );
172+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", 0 );
173+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", 0 );
174+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", 0 );
175+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", 0 );
176+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", 0 );
177+
}
178+
}
179+
}
180+
@@ -2444,25 +2444,25 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
181+
{
182+
if ( drm_supports_color_mgmt( drm ) )
183+
{
184+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
185+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", 0 );
186+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", 0 );
187+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", 0 );
188+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", 0 );
189+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
190+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", 0 );
191+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", 0 );
192+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", 0 );
193+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", 0 );
194+
}
195+
}
196+
197+
if ( drm_supports_color_mgmt( drm ) )
198+
{
199+
if (!g_bDisableBlendTF && !bSinglePlane)
200+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_BLEND_TF", drm->pending.output_tf );
201+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_BLEND_TF", drm->pending.output_tf );
202+
else
203+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_BLEND_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
204+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_BLEND_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
205+
206+
if (frameInfo->layers[i].ctm != nullptr)
207+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", frameInfo->layers[i].ctm->blob );
208+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", frameInfo->layers[i].ctm->blob );
209+
else
210+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", 0 );
211+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", 0 );
212+
}
213+
}
214+
else
215+
@@ -2474,12 +2474,12 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
216+
217+
if ( drm_supports_color_mgmt( drm ) )
218+
{
219+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
220+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", 0 );
221+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", 0 );
222+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", 0 );
223+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_BLEND_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
224+
- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", 0 );
225+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
226+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", 0 );
227+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", 0 );
228+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", 0 );
229+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_BLEND_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
230+
+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", 0 );
231+
}
232+
}
233+
}
234+
@@ -2575,17 +2575,17 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
235+
if ( !g_bDisableRegamma && !bSinglePlane )
236+
{
237+
drm->pending.output_tf = g_bOutputHDREnabled
238+
- ? DRM_VALVE1_TRANSFER_FUNCTION_PQ
239+
- : DRM_VALVE1_TRANSFER_FUNCTION_SRGB;
240+
+ ? AMDGPU_TRANSFER_FUNCTION_PQ_EOTF
241+
+ : AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF;
242+
}
243+
else
244+
{
245+
- drm->pending.output_tf = DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
246+
+ drm->pending.output_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
247+
}
248+
}
249+
else
250+
{
251+
- drm->pending.output_tf = DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
252+
+ drm->pending.output_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
253+
}
254+
255+
uint32_t flags = DRM_MODE_ATOMIC_NONBLOCK;
256+
@@ -2666,9 +2666,9 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
257+
if (ret < 0)
258+
return ret;
259+
}
260+
- if (crtc->has_valve1_regamma_tf)
261+
+ if (crtc->has_amd_regamma_tf)
262+
{
263+
- int ret = add_crtc_property(drm->req, crtc, "VALVE1_CRTC_REGAMMA_TF", 0);
264+
+ int ret = add_crtc_property(drm->req, crtc, "AMD_CRTC_REGAMMA_TF", 0);
265+
if (ret < 0)
266+
return ret;
267+
}
268+
@@ -2719,9 +2719,9 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
269+
return ret;
270+
}
271+
272+
- if (drm->crtc->has_valve1_regamma_tf)
273+
+ if (drm->crtc->has_amd_regamma_tf)
274+
{
275+
- ret = add_crtc_property(drm->req, drm->crtc, "VALVE1_CRTC_REGAMMA_TF", drm->pending.output_tf);
276+
+ ret = add_crtc_property(drm->req, drm->crtc, "AMD_CRTC_REGAMMA_TF", drm->pending.output_tf);
277+
if (ret < 0)
278+
return ret;
279+
}
280+
@@ -2763,9 +2763,9 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
281+
return ret;
282+
}
283+
284+
- if ( drm->crtc->has_valve1_regamma_tf && drm->pending.output_tf != drm->current.output_tf )
285+
+ if ( drm->crtc->has_amd_regamma_tf && drm->pending.output_tf != drm->current.output_tf )
286+
{
287+
- int ret = add_crtc_property(drm->req, drm->crtc, "VALVE1_CRTC_REGAMMA_TF", drm->pending.output_tf );
288+
+ int ret = add_crtc_property(drm->req, drm->crtc, "AMD_CRTC_REGAMMA_TF", drm->pending.output_tf );
289+
if (ret < 0)
290+
return ret;
291+
}
292+
diff --git a/src/drm.hpp b/src/drm.hpp
293+
index 6810797..bc0befb 100644
294+
--- a/src/drm.hpp
295+
+++ b/src/drm.hpp
296+
@@ -150,7 +150,7 @@ struct crtc {
297+
bool has_degamma_lut;
298+
bool has_ctm;
299+
bool has_vrr_enabled;
300+
- bool has_valve1_regamma_tf;
301+
+ bool has_amd_regamma_tf;
302+
303+
struct {
304+
bool active;
305+
@@ -212,19 +212,22 @@ struct fb {
306+
std::atomic< uint32_t > n_refs;
307+
};
308+
309+
-enum drm_valve1_transfer_function {
310+
- DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT,
311+
-
312+
- DRM_VALVE1_TRANSFER_FUNCTION_SRGB,
313+
- DRM_VALVE1_TRANSFER_FUNCTION_BT709,
314+
- DRM_VALVE1_TRANSFER_FUNCTION_PQ,
315+
- DRM_VALVE1_TRANSFER_FUNCTION_LINEAR,
316+
- DRM_VALVE1_TRANSFER_FUNCTION_UNITY,
317+
- DRM_VALVE1_TRANSFER_FUNCTION_HLG,
318+
- DRM_VALVE1_TRANSFER_FUNCTION_GAMMA22,
319+
- DRM_VALVE1_TRANSFER_FUNCTION_GAMMA24,
320+
- DRM_VALVE1_TRANSFER_FUNCTION_GAMMA26,
321+
- DRM_VALVE1_TRANSFER_FUNCTION_MAX,
322+
+enum amdgpu_transfer_function {
323+
+ AMDGPU_TRANSFER_FUNCTION_DEFAULT,
324+
+ AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,
325+
+ AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,
326+
+ AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,
327+
+ AMDGPU_TRANSFER_FUNCTION_IDENTITY,
328+
+ AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,
329+
+ AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,
330+
+ AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,
331+
+ AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,
332+
+ AMDGPU_TRANSFER_FUNCTION_BT709_OETF,
333+
+ AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,
334+
+ AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,
335+
+ AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,
336+
+ AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,
337+
+ AMDGPU_TRANSFER_FUNCTION_COUNT
338+
};
339+
340+
struct drm_t {
341+
@@ -267,7 +270,7 @@ struct drm_t {
342+
uint32_t shaperlut_id[ EOTF_Count ];
343+
enum drm_screen_type screen_type = DRM_SCREEN_TYPE_INTERNAL;
344+
bool vrr_enabled = false;
345+
- drm_valve1_transfer_function output_tf = DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
346+
+ amdgpu_transfer_function output_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
347+
} current, pending;
348+
bool wants_vrr_enabled = false;
349+

‎spec_files/gamescope/gamescope.spec

+13-5
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,18 @@ URL: https://github.com/ValveSoftware/gamescope
1010

1111
# Create stb.pc to satisfy dependency('stb')
1212
Source1: stb.pc
13-
Source2: chimeraos.patch
14-
Source3: crashfix.patch
15-
Source4: add_720p_var.patch
16-
Source5: touch_gestures_env.patch
17-
Source6: legion_go.patch
13+
14+
# https://github.com/ValveSoftware/gamescope/pull/1149
15+
Source2: amd_hdr.patch
16+
17+
# https://github.com/ChimeraOS/gamescope
18+
Source3: chimeraos.patch
19+
20+
# https://github.com/KyleGospo/gamescope
21+
Source4: crashfix.patch
22+
Source5: add_720p_var.patch
23+
Source6: touch_gestures_env.patch
24+
Source7: legion_go.patch
1825

1926
BuildRequires: meson >= 0.54.0
2027
BuildRequires: ninja-build
@@ -82,6 +89,7 @@ patch -Np1 < %{SOURCE3}
8289
patch -Np1 < %{SOURCE4}
8390
patch -Np1 < %{SOURCE5}
8491
patch -Np1 < %{SOURCE6}
92+
patch -Np1 < %{SOURCE7}
8593

8694
%build
8795
cd gamescope

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