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alexey-bataevalexey-bataev
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[OPENMP]Fix PR50640: OpenMP target clause implicitly scaling loop bounds to uint64_t.
Need to add some conversions to suppress possible warning messages. Differential Revision: https://reviews.llvm.org/D105187
1 parent 2f79acb commit 3eb2158

11 files changed

+1428
-1467
lines changed

‎clang/lib/Sema/SemaOpenMP.cpp

+13-3
Original file line numberDiff line numberDiff line change
@@ -9401,11 +9401,21 @@ checkOpenMPLoop(OpenMPDirectiveKind DKind, Expr *CollapseLoopCountExpr,
94019401

94029402
// Build expression: UB = min(UB, prevUB) for #for in composite or combined
94039403
// construct
9404+
ExprResult NewPrevUB = PrevUB;
94049405
SourceLocation DistEUBLoc = AStmt->getBeginLoc();
9405-
ExprResult IsUBGreater =
9406-
SemaRef.BuildBinOp(CurScope, DistEUBLoc, BO_GT, UB.get(), PrevUB.get());
9406+
if (!SemaRef.Context.hasSameType(UB.get()->getType(),
9407+
PrevUB.get()->getType())) {
9408+
NewPrevUB = SemaRef.BuildCStyleCastExpr(
9409+
DistEUBLoc,
9410+
SemaRef.Context.getTrivialTypeSourceInfo(UB.get()->getType()),
9411+
DistEUBLoc, NewPrevUB.get());
9412+
if (!NewPrevUB.isUsable())
9413+
return 0;
9414+
}
9415+
ExprResult IsUBGreater = SemaRef.BuildBinOp(CurScope, DistEUBLoc, BO_GT,
9416+
UB.get(), NewPrevUB.get());
94079417
ExprResult CondOp = SemaRef.ActOnConditionalOp(
9408-
DistEUBLoc, DistEUBLoc, IsUBGreater.get(), PrevUB.get(), UB.get());
9418+
DistEUBLoc, DistEUBLoc, IsUBGreater.get(), NewPrevUB.get(), UB.get());
94099419
PrevEUB = SemaRef.BuildBinOp(CurScope, DistIncLoc, BO_Assign, UB.get(),
94109420
CondOp.get());
94119421
PrevEUB =

‎clang/test/OpenMP/distribute_parallel_for_codegen.cpp

+138-144
Large diffs are not rendered by default.

‎clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp

+168-174
Large diffs are not rendered by default.

‎clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp

+32-34
Original file line numberDiff line numberDiff line change
@@ -18721,34 +18721,33 @@ int bar(int n){
1872118721
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1872218722
// CHECK1: omp.dispatch.cond:
1872318723
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18724-
// CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP9]] to i64
1872518724
// CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
18726-
// CHECK1-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP10]]
18725+
// CHECK1-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP10]] to i32
18726+
// CHECK1-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP9]], [[CONV7]]
1872718727
// CHECK1-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1872818728
// CHECK1: cond.true:
1872918729
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
18730+
// CHECK1-NEXT: [[CONV9:%.*]] = trunc i64 [[TMP11]] to i32
1873018731
// CHECK1-NEXT: br label [[COND_END:%.*]]
1873118732
// CHECK1: cond.false:
1873218733
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18733-
// CHECK1-NEXT: [[CONV9:%.*]] = sext i32 [[TMP12]] to i64
1873418734
// CHECK1-NEXT: br label [[COND_END]]
1873518735
// CHECK1: cond.end:
18736-
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP11]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ]
18737-
// CHECK1-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32
18738-
// CHECK1-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4
18736+
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[CONV9]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
18737+
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1873918738
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1874018739
// CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1874118740
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1874218741
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18743-
// CHECK1-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
18744-
// CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
18742+
// CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
18743+
// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1874518744
// CHECK1: omp.dispatch.body:
1874618745
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1874718746
// CHECK1: omp.inner.for.cond:
1874818747
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1874918748
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18750-
// CHECK1-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
18751-
// CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18749+
// CHECK1-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
18750+
// CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1875218751
// CHECK1: omp.inner.for.body:
1875318752
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1875418753
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
@@ -18765,20 +18764,20 @@ int bar(int n){
1876518764
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1876618765
// CHECK1: omp.inner.for.inc:
1876718766
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18768-
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP21]], 1
18769-
// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
18767+
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1
18768+
// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
1877018769
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1877118770
// CHECK1: omp.inner.for.end:
1877218771
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1877318772
// CHECK1: omp.dispatch.inc:
1877418773
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1877518774
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
18776-
// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
18777-
// CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_LB]], align 4
18775+
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
18776+
// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_LB]], align 4
1877818777
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1877918778
// CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
18780-
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
18781-
// CHECK1-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_UB]], align 4
18779+
// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
18780+
// CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_UB]], align 4
1878218781
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
1878318782
// CHECK1: omp.dispatch.end:
1878418783
// CHECK1-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -20328,34 +20327,33 @@ int bar(int n){
2032820327
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
2032920328
// CHECK2: omp.dispatch.cond:
2033020329
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20331-
// CHECK2-NEXT: [[CONV7:%.*]] = sext i32 [[TMP9]] to i64
2033220330
// CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
20333-
// CHECK2-NEXT: [[CMP8:%.*]] = icmp ugt i64 [[CONV7]], [[TMP10]]
20331+
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i64 [[TMP10]] to i32
20332+
// CHECK2-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP9]], [[CONV7]]
2033420333
// CHECK2-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2033520334
// CHECK2: cond.true:
2033620335
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
20336+
// CHECK2-NEXT: [[CONV9:%.*]] = trunc i64 [[TMP11]] to i32
2033720337
// CHECK2-NEXT: br label [[COND_END:%.*]]
2033820338
// CHECK2: cond.false:
2033920339
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20340-
// CHECK2-NEXT: [[CONV9:%.*]] = sext i32 [[TMP12]] to i64
2034120340
// CHECK2-NEXT: br label [[COND_END]]
2034220341
// CHECK2: cond.end:
20343-
// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP11]], [[COND_TRUE]] ], [ [[CONV9]], [[COND_FALSE]] ]
20344-
// CHECK2-NEXT: [[CONV10:%.*]] = trunc i64 [[COND]] to i32
20345-
// CHECK2-NEXT: store i32 [[CONV10]], i32* [[DOTOMP_UB]], align 4
20342+
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[CONV9]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
20343+
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2034620344
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2034720345
// CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
2034820346
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2034920347
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20350-
// CHECK2-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
20351-
// CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
20348+
// CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
20349+
// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2035220350
// CHECK2: omp.dispatch.body:
2035320351
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2035420352
// CHECK2: omp.inner.for.cond:
2035520353
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2035620354
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20357-
// CHECK2-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
20358-
// CHECK2-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20355+
// CHECK2-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
20356+
// CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2035920357
// CHECK2: omp.inner.for.body:
2036020358
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2036120359
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
@@ -20372,20 +20370,20 @@ int bar(int n){
2037220370
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2037320371
// CHECK2: omp.inner.for.inc:
2037420372
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
20375-
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP21]], 1
20376-
// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
20373+
// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1
20374+
// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
2037720375
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
2037820376
// CHECK2: omp.inner.for.end:
2037920377
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
2038020378
// CHECK2: omp.dispatch.inc:
2038120379
// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2038220380
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
20383-
// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
20384-
// CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_LB]], align 4
20381+
// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
20382+
// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_LB]], align 4
2038520383
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2038620384
// CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
20387-
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
20388-
// CHECK2-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_UB]], align 4
20385+
// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
20386+
// CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_UB]], align 4
2038920387
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
2039020388
// CHECK2: omp.dispatch.end:
2039120389
// CHECK2-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
@@ -21917,7 +21915,7 @@ int bar(int n){
2191721915
// CHECK3: omp.dispatch.cond:
2191821916
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2191921917
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
21920-
// CHECK3-NEXT: [[CMP4:%.*]] = icmp ugt i32 [[TMP9]], [[TMP10]]
21918+
// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
2192121919
// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2192221920
// CHECK3: cond.true:
2192321921
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
@@ -23463,7 +23461,7 @@ int bar(int n){
2346323461
// CHECK4: omp.dispatch.cond:
2346423462
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2346523463
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
23466-
// CHECK4-NEXT: [[CMP4:%.*]] = icmp ugt i32 [[TMP9]], [[TMP10]]
23464+
// CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
2346723465
// CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2346823466
// CHECK4: cond.true:
2346923467
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4

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