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A python implementation of an Assembler (defined ISA) and a simulator based on the binary generated by the ISA. It also provides the memory access trace w.r.t. cycles.

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CO M21 Assignment

Repository of group 10101102 for Computer Organization, Monsoon 2021 semester, assignment at IIITD.

About the repository

  • This repository contains an Assembler Simple-Assembler and a simulator SimpleSimulator.
  • The assembler converts a given code (pertaining to the ISA, refer to Assignment.pdf) to it's binary equivalent. It is also capable of reporting descriptive errors with the line number. (Also the error is colored 😄)
  • The simulator processes such binaries and dumps the program counter and the registers while the program is running, and after an hlt instruction, it dumps the state of the memory. It is important to note that we follow a Von-Neumann Architecture (unified memory | Instruction memory, hlt, followed by variables). It also plots the graph of memory access per cycle and is not capable of handling exceptions.
  • automated-testing is a testing suite designed to testify the correctness of outputs from the assembler and simulator. It contains the traces, binaries and a few assembly codes.
  • SimpleSimulator/plots/ contain all the plots generated by the simulator according to the timestamp (since epoch).

How to evaluate

  • Go to the automatedTesting directory and execute the run file with appropiate options passed as arguments.
  • Options available for automated testing:
    1. --verbose: Prints verbose output
    2. --no-asm: Does not evaluate the assembler
    3. --no-sim: Does not evaluate the simulator

How to run only the assembler or the simulator

  • Change directory to Simple-Assembler or SimpleSimulator.
  • Use ./run (on bash) and enter your assembly code or binary, after entering add a newline and press ctrl+D to terminate stdin.
  • Alternatively, you can directly run asm.py or samuelator.py.

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A python implementation of an Assembler (defined ISA) and a simulator based on the binary generated by the ISA. It also provides the memory access trace w.r.t. cycles.

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