Overview

It is intended to build a 32-bit:

• single cycle RISC-V processor;
• pipeline RISC-V processor;

Deploy the RISC-V core to the Xilinx Zynq-7000 AP SoC, integrated into the Zybo Z7 development board, by Digilent.

Tools

• Xilinx Vivado 2019.02
• Online RISC-V Interpreter
• Online RISC-V Assembler

Setup

Firstly, clone the repo:

$ git clone git@github.com:TomasLAbreu/riscv-processor.git
$ cd riscv-processor/

Create the single-cycle-risc-v processor Vivado project:

$ cd single-cycle-risc-v/
$ vivado &

When Vivado opens, go to Tools > Run Tcl Script... and run create_proj.tcl. Enjoy!

Create the pipeline-risc-v processor Vivado project:

$ cd pipeline-risc-v/
$ vivado &

When Vivado opens, go to Tools > Run Tcl Script... and run create_proj.tcl. Enjoy!

Support Documents

• RISC-V Instruction Set Specifications
• RISC-V Instruction Set Manual
• RISC-V Instruction Set Summary
• RISC-V Reference Card
• Digital Design and Computer Architecture RISC-V Edition - Chapter 7 (PDF pages 421-470)

Single-cycle Processor

Datapath and Control Unit Diagram

ALU

Pipeline Processor

Datapath, Control Unit and Hazard Unit Diagram

Supported instructions:

The RISC-V core supports the following ISA instructions:

I Type

• lb
• lh
• lw
• lbu
• lhu
• addi
• slli
• slti
• sltiu
• xori
• srli
• srai
• ori
• andi
• jalr

---

S Type

• sb
• sh
• sw

---

R Type

• add
• sub
• sll
• slt
• sltu
• xor
• srl
• sra
• or
• and

---

U Type

• auipc
• lui

---

B Type

• beq
• bne
• blt
• bge
• bltu
• bgeu

---

J Type

• jal

---

Done by:

• Tomás Abreu
• Diogo Fernandes
• Duarte Rodrigues
• João Miranda

Engenharia Eletrónica Industrial e Computadores @ Universidade do Minho, 2022