TDC2

1. From the IP catalog, select Integrated Logic Analyser

2. From Probe ports tab, create clkProp as probe0 and Btrig as probe1.

3. Follow the steps - https://vhdlwhiz.com/using-ila-and-vio/ to create a debug ILA core.

4. Open Vivado, go to File -> Project -> New

5. Give Project name and specify project location.

6. Select RTL Project(Deselect - Do not specify sources at this time, if selected)

7. Add all '.v' files provided in this repository.

8. Add '.xdc' file provided in this repository.

9. Select Arty A7 board.

10. Make sure top_level.v is selected as main file in sources.

11. From IP Catalog, search ILA. In general options -> change number of probes to 2. In Probe_Ports, change only probe0 width to 32.

12. Select Ok and Genrate ILA.

13. From Program and Debug, select Generate Bitstream (top right corner shows the ongoing operation).

14. Once finished, open Hardware Manager -> Open Target -> Auto Connect -> Program Device. It should show Digilent board, select this and program.

15. From ILA's Status window, select Run Trigger for this ILA, it will required generate waveforms.