RISC-V-CPU Core

Program using MyHDL to immitate a RISV CPU core.

The project contains the following CPU Models:

• Instruction fetch: Read instruction from memory
• Instruction decode: Understand what instruction means
• Execute: Perform the operation defined in instruction
• Memory access: Read required memory locations if needed
• Write back: Write the data to memory if modified

To run the program enter the following command in terminal::

• python riscv_cpu.py