Skip to content
View NickSica's full-sized avatar

Block or report NickSica

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. RISC-V-CPU Public

    A RISC-V CPU built in SystemVerilog for use in the DISCO Lab

    SystemVerilog 3

  2. fpga_cores Public

    VHDL 2 1

  3. dotfiles Public

    Shell

  4. MIPS-CPU Public

    MIPS CPU written in SystemVerilog

    VHDL 1

  5. ECEC621 Public

    For Drexel's ECEC412 and ECEC621 class

    C 1 1

32 contributions in the last year

Contribution Graph
Day of Week March April May June July August September October November December January February March
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
Less
No contributions.
Low contributions.
Medium-low contributions.
Medium-high contributions.
High contributions.
More

Contribution activity

March 2025

NickSica has no activity yet for this period.
Loading