APB Master-Slave Project

This project implements an APB (Advanced Peripheral Bus) master and slave interface in SystemVerilog. The master module controls APB transactions, while the slave module responds to read and write requests.

Project Structure

• rtl/ - Contains the RTL implementation.
  • apb_master.md - Documentation for the APB Master module.
  • apb_slave.md - Documentation for the APB slave module.

Future Work

Development of a verification environment for the APB master and slave. Simulation and validation of the APB protocol compliance.