Add Fetch L1 fence.i

SpinalHDL · Jan 19, 2024 · 28784e0 · 28784e0
1 parent a7f67f6
commit 28784e0
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Showing 2 changed files with 18 additions and 3 deletions.
diff --git a/src/main/scala/vexiiriscv/fetch/FetchL1Plugin.scala b/src/main/scala/vexiiriscv/fetch/FetchL1Plugin.scala
@@ -15,13 +15,15 @@ import vexiiriscv.misc._
 import vexiiriscv._
 import vexiiriscv.Global._
 import Fetch._
+import spinal.core.fiber.Retainer
 import vexiiriscv.riscv.CSR
 import vexiiriscv.schedule.ReschedulePlugin
 
 import scala.collection.mutable.ArrayBuffer
 
 
 trait FetchL1Service{
+  val invalidationRetainer = Retainer()
   val invalidationPorts = ArrayBuffer[FetchL1InvalidationBus]()
   def newInvalidationPort() = invalidationPorts.addRet(FetchL1InvalidationBus())
 }
@@ -164,6 +166,7 @@ class FetchL1Plugin(var translationStorageParameter: Any,
     }
 
     val invalidate = new Area {
+      invalidationRetainer.await()
       val cmd = Event
       cmd.valid := invalidationPorts.map(_.cmd.valid).orR
 
@@ -180,10 +183,11 @@ class FetchL1Plugin(var translationStorageParameter: Any,
         waysWrite.tag.loaded := False
       }
 
-      when(cmd.valid && canStart) {
+      when(done && cmd.valid && canStart) {
         counter := 0
       }
 
+      invalidationPorts.foreach(_.cmd.ready := False)
       when(!done){
         pp.fetch(readAt).haltIt()
         when(last){

diff --git a/src/main/scala/vexiiriscv/misc/TrapPlugin.scala b/src/main/scala/vexiiriscv/misc/TrapPlugin.scala
@@ -12,7 +12,7 @@ import vexiiriscv.riscv.Riscv._
 import vexiiriscv._
 import vexiiriscv.decode.Decode
 import vexiiriscv.decode.Decode.{INSTRUCTION_SLICE_COUNT, INSTRUCTION_SLICE_COUNT_WIDTH, INSTRUCTION_WIDTH}
-import vexiiriscv.fetch.{Fetch, InitService, PcService}
+import vexiiriscv.fetch.{Fetch, FetchL1Service, InitService, PcService}
 import vexiiriscv.memory.AddressTranslationService
 import vexiiriscv.schedule.Ages
 
@@ -96,14 +96,21 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
     val priv = host[PrivilegedPlugin]
     val cap = host[CsrAccessPlugin]
     val pp = host[PipelineBuilderPlugin]
+    val fl1p = host.get[FetchL1Service]
     val pcs = host[PcService]
     val ats = host[AddressTranslationService]
     val withRam = host.get[CsrRamService].nonEmpty
     val crs = withRam generate host[CsrRamService]
+    val fl1pLock = fl1p.map(_.invalidationRetainer())
     val buildBefore = retains(List(pp.elaborationLock, pcs.elaborationLock, cap.csrLock, ats.portsLock))
     val ramPortRetainers = withRam generate crs.portLock()
     awaitBuild()
 
+    val fetchL1Invalidate = fl1p.nonEmpty generate new Area{
+      val ports = (0 until HART_COUNT).map(hartId => fl1p.get.newInvalidationPort())
+      fl1pLock.get.release()
+    }
+
     val trapArgWidths = ArrayBuffer[Int](2)
     if(ats.mayNeedRedo) trapArgWidths += 2+ats.getStorageIdWidth()
     TRAP_ARG_WIDTH.set(trapArgWidths.max)
@@ -333,6 +340,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
             ).map(pending.state.code === _).orR
           )
 
+          fetchL1Invalidate.ports(hartId).cmd.valid := False
           PROCESS.whenIsActive{
             when(pending.state.exception || buffer.trap.interrupt) {
               goto(TRAP_TVAL)
@@ -348,7 +356,10 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
                   goto(XRET_EPC)
                 }
                 is(TrapReason.FENCE_I) {
-                  goto(JUMP) //TODO
+                  fetchL1Invalidate.ports(hartId).cmd.valid := True
+                  when(fetchL1Invalidate.ports(hartId).cmd.ready) {
+                    goto(JUMP) //TODO
+                  }
                 }
                 is(TrapReason.REDO) {
                   goto(JUMP)