Update LsuL1Plugin.scala

typo
SpinalHDL · Feb 13, 2024 · 7b1e9a0 · 7b1e9a0
1 parent 5c93969
commit 7b1e9a0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/vexiiriscv/execute/lsu/LsuL1Plugin.scala b/src/main/scala/vexiiriscv/execute/lsu/LsuL1Plugin.scala
@@ -768,7 +768,7 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
 
         val reservation = tagsWriteArbiter.create(2)
         val bankWriteReservation = bankWriteArbiter.create(2)
-//        val refillWayWithoutUpdate = CombInit(plruLogic.core.io.evict.id)
+        val refillWayWithoutUpdate = CombInit(plruLogic.core.io.evict.id)
         val refillWayNeedWriteback = WAYS_TAGS.map(w => w.loaded && withCoherency.mux(True, w.dirty)).read(refillWayWithoutUpdate)
 
         //Warning, those two signals aren't stable when lane.isFreezed