Add fetch cached wishbone support

SpinalHDL · Mar 5, 2025 · b7f2b11 · b7f2b11
1 parent ed738d8
commit b7f2b11
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Showing 4 changed files with 60 additions and 5 deletions.
diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
@@ -14,7 +14,7 @@ import vexiiriscv.execute._
 import vexiiriscv.execute.cfu.{CfuBusParameter, CfuPlugin, CfuPluginEncoding}
 import vexiiriscv.execute.fpu.{FpuAddSharedParam, FpuMulParam}
 import vexiiriscv.execute.lsu._
-import vexiiriscv.fetch.{FetchCachelessAxi4Plugin, FetchCachelessPlugin, FetchCachelessWishbonePlugin, FetchL1Axi4Plugin, FetchL1Plugin, PrefetcherNextLinePlugin}
+import vexiiriscv.fetch.{FetchCachelessAxi4Plugin, FetchCachelessPlugin, FetchCachelessWishbonePlugin, FetchL1Axi4Plugin, FetchL1Plugin, FetchL1WishbonePlugin, PrefetcherNextLinePlugin}
 import vexiiriscv.memory.{MmuPortParameter, MmuSpec, MmuStorageLevel, MmuStorageParameter, PmpParam, PmpPlugin, PmpPortParameter}
 import vexiiriscv.misc._
 import vexiiriscv.prediction.{LearnCmd, LearnPlugin}
@@ -742,6 +742,8 @@ class ParamSimple(){
       }
 
       if(fetchAxi4) plugins += new FetchL1Axi4Plugin()
+      if(fetchWishbone) plugins += new FetchL1WishbonePlugin()
+
     }
     plugins += new decode.DecodePipelinePlugin()
     plugins += new decode.AlignerPlugin(

diff --git a/src/main/scala/vexiiriscv/fetch/FetchL1Bridge.scala b/src/main/scala/vexiiriscv/fetch/FetchL1Bridge.scala
@@ -28,3 +28,12 @@ class FetchL1Axi4Plugin() extends FiberPlugin {
     val axi = master(fcp.logic.bus.toAxi4())
   }
 }
+
+class FetchL1WishbonePlugin() extends FiberPlugin {
+  val logic = during build new Area{
+    val fcp = host[FetchL1Plugin]
+    fcp.logic.bus.setAsDirectionLess()
+    val bus = master(fcp.logic.bus.toWishbone())
+  }
+}
+
diff --git a/src/main/scala/vexiiriscv/fetch/FetchL1Bus.scala b/src/main/scala/vexiiriscv/fetch/FetchL1Bus.scala
@@ -1,9 +1,6 @@
 package vexiiriscv.fetch
 
 import spinal.lib.misc.plugin.FiberPlugin
-
-
-
 import spinal.core._
 import spinal.lib._
 import spinal.lib.pipeline.Stageable
@@ -12,6 +9,7 @@ import spinal.lib.bus.tilelink
 import spinal.lib.bus.amba4.axilite.{AxiLite4Config, AxiLite4ReadOnly}
 import spinal.lib.bus.bmb.{Bmb, BmbAccessParameter, BmbParameter, BmbSourceParameter}
 import spinal.lib.bus.tilelink.{M2sSupport, SizeRange}
+import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
 import spinal.lib.misc.Plru
 
 import scala.collection.mutable.ArrayBuffer
@@ -63,6 +61,19 @@ case class FetchL1BusParam(physicalWidth : Int,
     useProt      = true,
     useStrb      = false
   )
+
+  def toWishboneConfig() = WishboneConfig(
+    addressWidth = physicalWidth-log2Up(dataWidth/8),
+    dataWidth = dataWidth,
+    selWidth = dataWidth/8,
+    useSTALL = false,
+    useLOCK = false,
+    useERR = true,
+    useRTY = false,
+    useBTE = true,
+    useCTI = true
+  )
+
 }
 
 /**
@@ -214,4 +225,34 @@ case class FetchL1Bus(p : FetchL1BusParam) extends Bundle with IMasterSlave {
     rsp.error := !axi.r.isOKAY()
     axi.r.ready := True
   }.axi
+
+
+  def toWishbone(): Wishbone = new Composite(this, "toWishbone"){
+    val wishboneConfig = p.toWishboneConfig()
+    val bus = Wishbone(wishboneConfig)
+    val counter = Reg(UInt(log2Up(p.lineSize*8/p.dataWidth) bits)) init(0)
+    val pending = counter =/= 0
+    val lastCycle = counter === counter.maxValue
+
+    bus.ADR := (cmd.address >> widthOf(counter) + log2Up(p.dataWidth/8)) @@ counter
+    bus.CTI := lastCycle ? B"111" | B"010"
+    bus.BTE := "00"
+    bus.SEL.setAll()
+    bus.WE  := False
+    bus.DAT_MOSI.assignDontCare()
+    bus.CYC := False
+    bus.STB := False
+    when(cmd.valid || pending){
+      bus.CYC := True
+      bus.STB := True
+      when(bus.ACK || bus.ERR){
+        counter := counter + 1
+      }
+    }
+
+    cmd.ready := cmd.valid && (bus.ACK || bus.ERR)
+    rsp.valid := RegNext(bus.CYC && (bus.ACK || bus.ERR)) init(False)
+    rsp.data := RegNext(bus.DAT_MISO)
+    rsp.error := RegNext(bus.ERR)
+  }.bus
 }
diff --git a/src/main/scala/vexiiriscv/tester/TestBench.scala b/src/main/scala/vexiiriscv/tester/TestBench.scala
@@ -364,12 +364,15 @@ class TestOptions{
     val fetchUncachedWishbone = dut.host.get[fetch.FetchCachelessWishbonePlugin].map { p =>
       mapFetchWishbone(p.logic.bridge.bus)
     }
+    val fetchCachedWishbone = dut.host.get[fetch.FetchL1WishbonePlugin].map { p =>
+      mapFetchWishbone(p.logic.bus)
+    }
 
     val fclp = dut.host.get[fetch.FetchCachelessPlugin].filter(!_.logic.bus.cmd.valid.isDirectionLess).map { p =>
       val bus = p.logic.bus
       val cmdReady = StreamReadyRandomizer(bus.cmd, cd)
 
-      case class Cmd(address: Long, id: Int)
+      case class Cmd(address : Long, id : Int)
       val pending = mutable.ArrayBuffer[Cmd]()
 
       val cmdMonitor = StreamMonitor(bus.cmd, cd) { p =>