MicroSoc add spiFlash

src/main/scala/vexiiriscv/soc/micro/MicroSoc.scala

@@ -3,7 +3,9 @@ package vexiiriscv.soc.micro
 import spinal.core._
 import spinal.core.fiber.Fiber
 import spinal.lib._
+import spinal.lib.bus.amba3.apb.Apb3
 import spinal.lib.bus.tilelink
+import spinal.lib.bus.tilelink.{M2sSupport, M2sTransfers}
 import spinal.lib.bus.tilelink.fabric.Node
 import spinal.lib.com.spi.ddr.{SpiXdrMasterCtrl, SpiXdrParameter}
 import spinal.lib.com.spi.xdr.TilelinkSpiXdrMasterFiber
@@ -56,22 +58,25 @@ class MicroSoc(p : MicroSocParam) extends Component {
       uart.node at 0x10001000 of bus32
       plic.mapUpInterrupt(1, uart.interrupt)
 
-      val spi = new TilelinkSpiXdrMasterFiber(SpiXdrMasterCtrl.MemoryMappingParameters(
+      val spiFlash = p.withSpiFlash generate new TilelinkSpiXdrMasterFiber(SpiXdrMasterCtrl.MemoryMappingParameters(
         SpiXdrMasterCtrl.Parameters(8, 12, SpiXdrParameter(2, 2, 1)).addFullDuplex(0,1,false),
         xipEnableInit = true,
         xip = SpiXdrMasterCtrl.XipBusParameters(addressWidth = 24, lengthWidth = 6)
-      ))
-      plic.mapUpInterrupt(2, spi.interrupt)
-      spi.ctrl at 0x10002000 of bus32
-      spi.xip at 0x20000000 of bus32
+      )){
+        plic.mapUpInterrupt(2, interrupt)
+        ctrl at 0x10002000 of bus32
+        xip at 0x20000000 of bus32
+      }
+
 
       val demo = p.demoPeripheral.map(new PeripheralDemoFiber(_){
         node at 0x10003000 of bus32
         plic.mapUpInterrupt(3, interrupt)
       })
 
-      val cpuPlic = cpu.bind(plic)
-      val cpuClint = cpu.bind(clint)
+      // Let's connect a few of the CPU interfaces to their respective peripherals
+      val cpuPlic = cpu.bind(plic) // External interrupts connection
+      val cpuClint = cpu.bind(clint) // Timer interrupt + time reference + stop time connection
     }
 
     val patcher = Fiber patch new Area{

src/main/scala/vexiiriscv/soc/micro/MicroSocGen.scala

@@ -43,7 +43,7 @@ object Bsp{
       }
     }
 
-    headerWriter.close
+    headerWriter.close()
   }
 }
 

src/main/scala/vexiiriscv/soc/micro/MicroSocParam.scala

@@ -12,6 +12,7 @@ class MicroSocParam {
   val vexii = new ParamSimple()
   var demoPeripheral = Option.empty[PeripheralDemoParam]
   val socCtrl = new SocCtrlParam()
+  var withSpiFlash = false
 
   // Provide some sane default
   vexii.fetchForkAt = 1
@@ -26,6 +27,7 @@ class MicroSocParam {
     import parser._
     opt[Int]("ram-bytes") action { (v, c) => ramBytes = v }
     opt[String]("ram-elf") action { (v, c) => ramElf = Some(new File(v)) }
+    opt[Boolean]("spi-flash") action { (v, c) => withSpiFlash = v  }
     opt[Map[String, String]]("demo-peripheral") action { (v, c) => demoPeripheral = Some(new PeripheralDemoParam(
       ledCount = v.getOrElse("leds", "8").toInt,
       buttonCount = v.getOrElse("buttons", "8").toInt

src/main/scala/vexiiriscv/soc/micro/MicroSocSim.scala

@@ -58,7 +58,7 @@ object MicroSocSim extends App{
       baudPeriod = uartBaudPeriod
     )
 
-    val flash = new FlashModel(dut.system.peripheral.spi.logic.spi, dut.socCtrl.system.cd)
+    val spiFlash = p.withSpiFlash generate new FlashModel(dut.system.peripheral.spiFlash.logic.spi, dut.socCtrl.system.cd)
 
     val konata = traceKonata.option(
       new vexiiriscv.test.konata.Backend(new File(currentTestPath, "konata.log")).spinalSimFlusher(hzToLong(1000 Hz))
@@ -81,7 +81,7 @@ object MicroSocSim extends App{
     if(elfFile != null) {
       val elf = new Elf(elfFile, p.vexii.xlen)
       elf.load(dut.system.ram.thread.logic.mem, 0x80000000l, true)
-      elf.loadArray(flash.content, 0x20000000l, true)
+      if(p.withSpiFlash) elf.loadArray(spiFlash.content, 0x20000000l, true)
       probe.backends.foreach(_.loadElf(0, elfFile))
     }
   }