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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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  4. riscv-dv riscv-dv Public

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

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  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

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Repositories

Showing 10 of 109 repositories
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 265 Apache-2.0 79 19 1 Updated Mar 4, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,180 Apache-2.0 616 324 (1 issue needs help) 159 Updated Mar 4, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 104 Apache-2.0 51 113 50 Updated Mar 4, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 83 Apache-2.0 45 86 16 Updated Mar 4, 2025
  • synlig Public

    SystemVerilog synthesis tool

    chipsalliance/synlig’s past year of commit activity
    Verilog 180 Apache-2.0 24 69 11 Updated Mar 4, 2025
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 9 Apache-2.0 2 12 5 Updated Mar 4, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 14 Apache-2.0 3 11 1 Updated Mar 4, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 3 0 0 Updated Mar 4, 2025
  • UHDM Public

    Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/UHDM’s past year of commit activity
    C++ 209 Apache-2.0 40 16 0 Updated Mar 4, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 12 Apache-2.0 8 28 9 Updated Mar 4, 2025
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