cores: uart.py: slice data in fsm run #2206
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slice data in fsm run Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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Thanks @maass-hamburg, we were here relying on verilog properties, was it causing an issue with a specific project/toolchain? (I'm asking since this property is probably used in various place). |
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@enjoy-digital it was not really causing a problem, just wanting to remove a warning: |
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OK thanks, this is merged. |
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slice data in fsm run