PR following enjoy-digital#2200 closure #2210
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Hello,
I found in the now resolved #2200 that the mapping of some JTAG instruction ports in litex/litex/soc/cores/cpu/naxriscv/core.py are not matching the name of the actual NaxRiscv's JTAG instruction ports.
Following the discussion in #2200, here is how it could be adressed.
Best regards,