Add Linux support for CVA5, including PLIC and CLINT and major bug fixes

[mohammadshahidzade]

This pull request introduces key changes to enable Linux support on the CVA5 core, including the addition of PLIC and CLINT, which required modifications to isr.c. It also resolves the original interrupt issue and includes initial changes necessary for running an operating system on multicore CVA5.

Key Updates:

• Full support for the 20240411 RISC-V privileged architecture (previously, only a draft spec from ~2017-2019 was supported).
• New separate TLBs for instructions and data.
• Sv32 virtual memory support.
• Significant bug fixes for interrupt and exception handling. This resolves issue Adding paths for vivado. #19 (Interrupts can lead to MEPC inconsistent with register state).
• RISC-V atomic extension (AMO) support, resolving issue Allow using gcc for or1k. #21 (State of AMO support).
• Simulation support for the latest Verilator version.
• Multicore support with cache snooping, validated on configurations with 1, 2, and 4 cores.
• Optimized PLIC and CLINT implementation, required for full multicore Linux support.
• Validated on FPGA boards, including VCU118 and Digilent Nexys.
• Performance: Achieves up to 250 MHz on the VCU118 (single-core).
• Software compatibility tested with Linux 5.18.0 and OpenSBI v0.8-2-ga9ce3ad.

These changes are based on PR #29 from openhwgroup/cva5. Let me know if any refinements are needed!

[mohammadshahidzade]

Hi,
I also updated the python repo in this pull request litex-hub/pythondata-cpu-cva5#1