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[InstCombine] Fold shift+cttz with power of 2 operands #127055

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Feb 18, 2025
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[InstCombine] Fold shift+cttz with power of 2 operands #127055

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9f70feb
[InstCombine] Fold cttz with power of 2 operands
MDevereau Feb 13, 2025
c26fff8
Add fold for zero
MDevereau Feb 13, 2025
4c2004a
Remove unnecessary line
MDevereau Feb 17, 2025
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17 changes: 9 additions & 8 deletions llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1614,18 +1614,19 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
return Overflow;

// Transform ((pow2 << x) >> cttz(pow2 << y)) -> ((1 << x) >> y)
Value *Shl0_Op0, *Shl0_Op1, *Shl1_Op0, *Shl1_Op1;
Value *Shl0_Op0, *Shl0_Op1, *Shl1_Op1;
BinaryOperator *Shl1;
if (match(Op0, m_Shl(m_Value(Shl0_Op0), m_Value(Shl0_Op1))) &&
match(Op1, m_Intrinsic<Intrinsic::cttz>(m_BinOp(Shl1))) &&
match(Shl1, m_Shl(m_Value(Shl1_Op0), m_Value(Shl1_Op1))) &&
isKnownToBeAPowerOfTwo(Shl1, false, 0, SQ.getWithInstruction(&I).CxtI) &&
Shl0_Op0 == Shl1_Op0) {
match(Shl1, m_Shl(m_Specific(Shl0_Op0), m_Value(Shl1_Op1))) &&
isKnownToBeAPowerOfTwo(Shl0_Op0, /*OrZero=*/true, 0, &I)) {
auto *Shl0 = cast<BinaryOperator>(Op0);
if ((Shl0->hasNoUnsignedWrap() && Shl1->hasNoUnsignedWrap()) ||
(Shl0->hasNoSignedWrap() && Shl1->hasNoSignedWrap())) {
Value *NewShl =
Builder.CreateShl(ConstantInt::get(Shl1->getType(), 1), Shl0_Op1);
bool HasNUW = Shl0->hasNoUnsignedWrap() && Shl1->hasNoUnsignedWrap();
bool HasNSW = Shl0->hasNoSignedWrap() && Shl1->hasNoSignedWrap();
if (HasNUW || HasNSW) {
Value *NewShl = Builder.CreateShl(ConstantInt::get(Shl1->getType(), 1),
Shl0_Op1, "", HasNUW, HasNSW);
Builder.CreateShl(ConstantInt::get(Shl1->getType(), 1), Shl0_Op1);
return BinaryOperator::CreateLShr(NewShl, Shl1_Op1);
}
}
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24 changes: 10 additions & 14 deletions llvm/test/Transforms/InstCombine/shift-cttz-ctlz.ll
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Expand Up @@ -110,11 +110,11 @@ define i64 @fold_cttz_64() vscale_range(1,16) {
; CHECK-NEXT: ret i64 4
;
entry:
%0 = tail call i64 @llvm.vscale.i64()
%1 = shl nuw nsw i64 %0, 4
%2 = shl nuw nsw i64 %0, 2
%3 = tail call range(i64 2, 65) i64 @llvm.cttz.i64(i64 %2, i1 true)
%div1 = lshr i64 %1, %3
%vscale = tail call i64 @llvm.vscale.i64()
%shl0 = shl nuw nsw i64 %vscale, 4
%shl1 = shl nuw nsw i64 %vscale, 2
%cttz = tail call range(i64 2, 65) i64 @llvm.cttz.i64(i64 %shl1, i1 true)
%div1 = lshr i64 %shl0, %cttz
ret i64 %div1
}

Expand All @@ -125,16 +125,12 @@ define i32 @fold_cttz_32() vscale_range(1,16) {
; CHECK-NEXT: ret i32 4
;
entry:
%0 = tail call i32 @llvm.vscale.i32()
%1 = shl nuw nsw i32 %0, 4
%2 = shl nuw nsw i32 %0, 2
%3 = tail call range(i32 2, 65) i32 @llvm.cttz.i32(i32 %2, i1 true)
%div1 = lshr i32 %1, %3
%vscale = tail call i32 @llvm.vscale.i32()
%shl0 = shl nuw nsw i32 %vscale, 4
%shl1 = shl nuw nsw i32 %vscale, 2
%cttz = tail call range(i32 2, 65) i32 @llvm.cttz.i32(i32 %shl1, i1 true)
%div1 = lshr i32 %shl0, %cttz
ret i32 %div1
}

declare i64 @llvm.vscale.i64()
declare i64 @llvm.cttz.i64(i64, i1 immarg)
declare i32 @llvm.vscale.i32()
declare i32 @llvm.cttz.i32(i32, i1 immarg)
declare void @use(i32)