⚡ KCP - A Fast and Reliable ARQ Protocol

A lightweight well-featured CLI downloader optimized for speed and early preview.

A benchmarking suite for heterogeneous systems. The primary goal of this project is to improve and update aspects of existing benchmarking suites which are either insufficient or outdated.

High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

Accelerator for Hyperdimensional Computing (HDC)

68000 Relocator with FLASH Kickstart

Amiga 600 Accelerator And RAM Expansion

POWER9 gzip engine documentation and code samples

SmartTLS is the project introduced at the paper "A Case for SmartNIC-accelerated Private Communication" (APNET 20). It accelerates web servers by offloading TLS handshake protocol into network card (NIC).

2023年全国大学生集成电路创新创业大赛-海运捷讯杯-全国二等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition

Example program demonstrating the use of the Revere-AMU System Architecture from userspace, with VFIO

This version of crispy-DOOM uses 8 HW accelerators on the FPGA

[FCCM 2019] Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU

This project represents a structured and comprehensive implementation of a hardware accelerator for the Histogram of Oriented Gradients (HOG) algorithm, specifically tailored for face detection.

FPGA-based accelerator for compactions in LSM-tree based KV stores. Making compaction great again, again!

Deploying_CNN_on_DE10nano_using_OpenCL

Accelerated 3-dimensional stencil code

The purpose of this project was to design an accelarator using C and design tools from Xilinx, like the Vivado High level Synthesis for the inner design of the Accelarator and the SDSoC to design the transfer of the data in Zynq-7000.

Short exercises for GPU at Complutense University of Madrid. Mirror from GitLab