RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
riscv microprocessor computer-architecture vlsi risc-v tlv riscv32 processor-design riscv32i computer-hardware
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Updated
Apr 29, 2022 - Python