#
instruction-level-parallelism
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Super scalar Processor design
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Sep 7, 2014
Verilog
Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals
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Mar 3, 2025
TypeScript
Superscalar dual-issue RISC-V processor
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Jul 31, 2024
SystemVerilog
Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm
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Mar 24, 2019
VHDL
Curriculum material for teaching computer architecture with MIPS and POWER
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Feb 10, 2024
Python
Project for 2023/2024 - Computer Organization @ IST
Redesigned the RNBIP single-bus architecture to implement a 3 stage instruction-level pipeline.
Updated
Sep 25, 2020
Verilog
ECE552: Computer Architecture — Fall 2020.
Examples of OpenMP for instruction-level parallelism.
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