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rtl

Here are 56 public repositories matching this topic...

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Feb 26, 2025
Python

siliconcompiler / siliconcompiler

Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

Updated Apr 5, 2025
Python

eldraco / Salamandra

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

python threshold microphone sound rtl sdr microphones spy spy-microphones salamandra find-microphones detect-microphones

Updated Jan 11, 2021
Python

pymtl / pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

python rtl verilog systemverilog hdl open-source-hardware pymtl hardware-generation open-source-eda multi-level-modeling cycle-level-modeling

Updated Mar 12, 2025
Python

Nic30 / hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

simulator fpga compiler hls vhdl rtl verilog hcl codegenerator codegen systemverilog systemc uvm

Updated Nov 23, 2024
Python

wal

ics-jku / wal

WAL enables programmable waveform analysis.

hardware verification eda rtl

Updated Feb 26, 2025
Python

PrincetonUniversity / AutoSVA

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

design verification rtl verilog systemverilog sva methodology-development

Updated Mar 29, 2024
Python

RamezIssac / django-tabular-permissions

Display Django permissions in a HTML table that is translatable and easily customized.

django admin widget permissions rtl translatable

Updated Apr 20, 2024
Python

klohner / honeywell-wireless-doorbell

Understanding the RF signal used in the Honeywell RCWL300A, RCWL330A, Series 3, 5, 9 and Decor Series Wireless Chimes

doorbell rtl honeywell rfcat yardstick rtl-433

Updated Apr 12, 2021
Python

hdl-registers

hdl-registers / hdl-registers

An open-source HDL register code generator fast enough to run in real time.

python c html asic generator fpga cplusplus register vhdl eda rtl csr axi axi-lite register-interface

Updated Apr 5, 2025
Python

sphinxcontrib-hdl-diagrams

SymbiFlow / sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

documentation fpga sphinx documentation-tool rtl verilog diagrams hdl yosys sphinx-extension symbiflow

Updated Sep 25, 2023
Python

scutdig / PyChip-py-hcl

A Hardware Construct Language

python python3 rtl firrtl verilog hardware-designs

Updated Jul 25, 2022
Python

Nic30 / hwtLib

hardware library for hwt (= ipcore repo)

fpga vhdl rtl verilog hardware-designs

Updated Nov 21, 2024
Python

mohamed / fsm2sv

SystemVerilog FSM generator

hardware rtl systemverilog

Updated May 5, 2024
Python

Intuity / nexus

Open source RTL simulation acceleration on commodity hardware

hardware simulation rtl verilog systemverilog hardware-acceleration hardware-accelerator hardware-accelerators

Updated Apr 13, 2023
Python

sphinx-verilog-domain

SymbiFlow / sphinx-verilog-domain

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

sphinx rtl verilog systemverilog hdl verilog-library sphinx-extension sphinx-domain

Updated Mar 1, 2021
Python

RedhawkSDR / RTL2832U

A frontendInterfaces compliant device for the RTL2832U usb dongle

rtl sdr redhawk

Updated Sep 24, 2019
Python

tsfpga

tsfpga / tsfpga

A flexible and scalable development platform for modern FPGA projects.

asic fpga ci simulation test vhdl build-automation eda test-automation rtl verilog xilinx synthesis vivado systemverilog implementation vunit

Updated Apr 3, 2025
Python

10x-Engineers / Infinite-ISP_ReferenceModel

A Python based fixed-point implementation of the Infinite-ISP design for ASIC and FPGA design and verification.

computer-vision image-processing rtl isp camera-pipeline image-signal-processing

Updated Feb 6, 2025
Python

freand76 / digsim

An interactive digital logic simulator with verilog support (Yosys)

python simulator simulation logic rtl verilog yosys vcd

Updated Feb 23, 2025
Python

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