Repurposing existing HDL tools to help writing better code

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Example of Python and PyTest powered workflow for a HDL simulation

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

Practice Codes of SystemVerilog Language

I am trying to develop my skills through daily practice and consistency.

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

This repo contains a mini-processor design implemented on FPGA using verilog

This repo contains an I2C transaction state machine modelled in Verilog targeted for the Zynq Zedboard

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

Includes lab exercises from my Computer Organization and Digital Design module. It features implementations of various components inside a processor using VHDL . Finally I make 4 bit nanoprocessor combining all components those build in previous labs.

A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board

Digital design fundamentals - a 3rd year CSE banchelor course in ITMO University