open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn't define TrustZone-like primitives to provide hardware separation. To shield critical functionality from untrusted third-party components, MultiZone provides hardware-enforced, software-defined separation of multi

Simple, zero-copy DMA to/from userspace.

Autonomous pre-boot DMA attack hardware implant for M.2 slot based on PicoEVB development board

C code to parse xilinx bitstream. See http://lastweek.io/fpga/bitstream/

The open-source Zynq 7000 BSP generator for openXC7

SPI ELF bootloader for Xilinx Microblaze processors

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

Run ethash opencl kernel on Xilinx's Alveo U50

Xilinx Zynq SoC based all-in-one quadrocopter flight controller. Stereo 720p side-by-side digital video transmission.

Matrix Multiplication in Hardware

Xilinx Bitstream Format Library. Easily read .bit files from C programs.

Notes on the Eclypse Z7 development board

Real-Time Operating System (RTOS) for Xilinx Zynq-7000 Cortex-A9 (ARMv7-A) multi-core SoCs (ZedBoard, PicoZed, MicroZed and similars) based on the ARINC 653 Part 1 specification

FPGA Acceleration for the LoFreq variant caller

ILI9488 TFT SPI display library for Xilinx SoC and FPGA

Spartan Edge Accelerator dev board console extensions