Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

Verification IP for AMBA APB Protocol

APB4 Multiplexor

APB master and slave developed in RTL.

General Purpose IO with APB4 interface

Common SystemVerilog RTL modules for RgGen

APB verification using UVM

APB verification based on Universal verification Method

GCD calculator with APB Slave interface.

Implement APB interface for I2C communication

design-and-verification-of-MCDF-phase3

A presentation about Advanced Microcontroller Bus Architecture

This project implements an Advanced Peripheral Bus (APB) Master and Slave in SystemVerilog. The APB Master initiates read/write transactions, while the APB Slave responds to these transactions and handles memory access. A dedicated verification environment is provided for each part of the design, including testbenches for the APB Master and Slave.

This is a bus functional model of Advanced Peripheral Bus.

Basic APB-compatible module designed for use with Verilator, but should work with any DPI-C compatible simulator.