Generator for CRC HDL code (VHDL, Verilog, MyHDL)

Python implementation of a Hardware Description Language (HDL)

Myhdl fork that includes support for multiple entities (MEP110) and fixed point functionality (MEP 111) on VHDL. See myhdl/numeric dir under the numeric branch, and the Cordic example (example/cordic/Cordic.ipynb).

RISCV CPU core

This is a simple CPU using myHDL package.